Fairly Fast & Flexible Reed-Solomon Coding
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Updated
Feb 4, 2024 - C++
Fairly Fast & Flexible Reed-Solomon Coding
FaultSim is a memory reliability simulator for 2D and 3D systems. FaultSim is created with the joint effort of Georgia Tech and AMD Inc -- ACM-TACO 2015
A collection of applied DSP methods for Wireless Communication Systems
Error correction code implementations in CoCoALib
Error Correcting Codes - Binary Convolutional Code
This program was designed to illustrate how the Hamming code is being implemented in detecting and correcting code.
Fast C++17 Simulation Tool for LDPC Codes with Multithreading Support
Implementation of error correction codes (ECC) in C++
Upper bound on code distance of QC-LDPC codes based on MacKay-Vontobel-Smarandache
Parallel implementation of MSVBS ( MacKay-Smarandache-Vontobel-Butler-Siegel) upper bound estimation of code distance ( Hamming distance) using MPI (multi tread CPU and Cluster)
AVX implementation of different LDPC decoders MS NMS SCMS SCSP under floor/layer schedulers
Floor-scale modular lifting of MET-LDPC with estimation Upper bound on Code distance optimization and EMD for construction length adaptive codes
Tool-chain to construct Length and Rate adaptive MET QC-LDPC Codes using EMD Spectrum and Hamming distance optimization
HARP is a memory error profiling algorithm (i.e., for identifying error-prone cells) designed for use with memory chips that use on-die error-correcting codes (ECC). This tool uses Monte-Carlo simulation to evaluate HARP and other error profilers. HARP and this tool are described in the 2021 MICRO paper by Patel et al.: https://arxiv.org/abs/210…
Linear programming based Stopping sets enumerator for regular and irregular QC-LDPC codes
Enumerate LDPC Codes extrinsic message degree (EMD) Spectrum for analyzing cycles properties sublinear and part of linear trapping sets
DRAM error-correction code (ECC) simulator incorporating statistical error properties and DRAM design characteristics for inferring pre-correction error characteristics using only the post-correction errors. Described in the 2019 DSN paper by Patel et al.: https://people.inf.ethz.ch/omutlu/pub/understanding-and-modeling-in-DRAM-ECC_dsn19.pdf.
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