OpenGL 1.x implementation for FPGAs
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Updated
Jun 1, 2024 - C++
OpenGL 1.x implementation for FPGAs
This project implements a convolution kernel based on vivado HLS on zcu104
Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)
EXPERIMENTAL Verilog (and HLS, C++, Python, OpenCL) implementation of the RC4 stream cipher.
Predicting 3D human pose from single image using a VCK5000 Versal Development Card
A lightweight cloudFPGA prototype for processor simulation. It provides online scalable route resources with only open source synthesis toolset.
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
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