Repository to store all design and testbench files for Senior Design
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Updated
Apr 16, 2020 - Verilog
Repository to store all design and testbench files for Senior Design
Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown and Spectre)
Reproduction of https://github.com/DfX-NYUAD/GNNUnlock
This project is a modified verison of the OpenRISC 1200 open-source processor, designed to estimate the feasibility of using an On-Chip Software Obfuscator to reduce the controllability over software activated Hardware Trojans.
Supporting material for our RL-based Trojan insertion work at CCS 2022.
Some generic probabilistic methodologies to identify hardware trojans in arbitrary hardware designs
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