Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
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Updated
Jun 16, 2024 - C
Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that reads integers input on the switches sequentially, adds them up and displays them on the 7 segment diaplay. Demonstrates Microblaze, AXI and AXI streams.
C library for shared memory and messaging using inter processor interrupts.
This will be my starting point for learning microblaze softcore processor
MSc. (DSE UoY) project documentation and partial source code
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