SUSTech CS202/CS214 Computer Organization Project. Streams Bad Apple.
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Updated
Dec 11, 2023 - SystemVerilog
SUSTech CS202/CS214 Computer Organization Project. Streams Bad Apple.
A complete hardware description of a pipeline MIPS processor in SystemVerilog that can execute integer assembly code implemented on the Altera DE2-115 FPGA. It also has the ALMa Mips Mounter built-in.
MIPS Single cycle Verilog Implementation
MIPS multi cycle Verilog Implementation
Single-cycle single-core MIPS processor
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