Opensource DDR3 Controller
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Updated
Jun 29, 2024 - Verilog
Opensource DDR3 Controller
External PHY RTL8201F with HR871181A
External PHY RTL8201F with switch RTL8305NB and 2xHR871181A
Neural Signal Analysis
P8X32A/Propeller, P2X8C4M64P/Propeller 2 driver object for the ENC28J60 Ethernet Controller
An FPGA-based MII to RMII & SMII converter to connect 100M ethernet PHY chip such as LAN8720 or KSZ8041TLI-S. 基于FPGA的MII转RMII和MII转SMII,用来连接LAN8720、KSZ8041TLI-S等百兆以太网PHY芯片。
Go package for parsing Source Engine StudioModel formats (.mdl, .vtx, .vvd, .phy)
BRAVE is a collaborative research project started in January 2018, that aims at creating new physical-layer (PHY) techniques devoted to beyond-5G wireless communications. The partners (Siradel, Central-Supélec, CEA-Leti and ANFR) are designing new high-data-rate and energy-efficient waveforms that operate in frequencies above 90 GHz. Application…
P2X8C4M64P/Propeller 2 driver object for the LAN8720 Ethernet PHY
an 100% python navigator
Python module for 5G NR sync signals and decoding.
Converts moutainsorted clusters to phy for curation using SpikeInterface. Includes a plugin to add mountainsort cluster metrics to phy.
Analysis of physical layer security of MIMO system using Machine Learning algorithms vs theoretical best
Plugins for the manual spike sorting program phy
Open Sigfox Stack Reference Implementation - Physical Layer for SDR
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