This is a MIPS 5 stage 32-bit pipelined processor with Harvard architecture, which comes with an assembler to interpret instructions to supported OP codes.
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Updated
Aug 12, 2021 - VHDL
This is a MIPS 5 stage 32-bit pipelined processor with Harvard architecture, which comes with an assembler to interpret instructions to supported OP codes.
A simple 5-stage pipelined processor following Harvard's architecture. The processor has RISC-like ISA. There are eight 2-byte general-purpose registers, and another three special-purpose registers (Program Counter, Exception Program Counter, Stack Pointer). The memory address space is 1 MB of 16-bit width and is word addressable.
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Standard five-stage pipelined 32-bit MIPS processor with hazard detection
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