32-bit Superscalar RISC-V CPU
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Updated
Sep 18, 2021 - Verilog
32-bit Superscalar RISC-V CPU
An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) of UM-SJTU JI.
5 stages RISC pipelined processor following Harvard architecture.
Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.
Digital Systems 2 Course [ECE 778] - CA4 - Spring 2023 - University of Tehran - Dr. Safari
Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding cont…
This repository is created to build a single cycle processor and converting it to a 5-stage pipelined processor capable of executing a bubble sort program.
The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.
High-level block designs for MIPS 32 bit processor with pipelining & forwarding controls, hazard detection, and timing. Tested and verified in EECS 112L course on Organization of Computers.
Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor
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