Super scalar Processor design
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Updated
Sep 7, 2014 - Verilog
Super scalar Processor design
Single Bus Processor - Summer Project 2016
CZ3001 Advanced Computer Architecture, AY 2015-16 Semester 1
MIPS processor simulated in behavioral Verilog
CSE Bubble developed as semester project for Computer Organisation (CS220) course in 4th semester
"Introduction to FPGA and Verilog" at MIPT DREC
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