soc
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SideLine is a software-based power side-channel analysis vector. It uses delay-lines (located in SoC memory controllers) as power meters.
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Nov 24, 2020 - HTML
Repository for our 2022 SOC Healthy NYC data requests
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Sep 12, 2022 - HTML
Pipelining and timing issues in CPU data-paths. Principles of RISC-type CPU instruction set and architecture. Structural, data and control hazards in a RISC processor, forwarding loops, branch mechanisms. Memory architectures in CPUs such as register files and caches. UART, I2C protocols.
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Feb 12, 2021 - HTML
This repository is a group-project related to the class: IDG1293 - Avansert CSS
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May 3, 2021 - HTML
Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedded programs targeted at the microprocessor to control the peripherals
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Nov 24, 2023 - HTML
Awesome list of keywords and artifacts for Threat Hunting sessions
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May 31, 2024 - HTML
学习安全运营的记录 | The knowledge base of security operation
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Aug 27, 2023 - HTML
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