A repository where I intend to upload most Hardware design projects I make.
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Updated
Jun 28, 2022 - SystemVerilog
A repository where I intend to upload most Hardware design projects I make.
DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow video controller with alpha-blended layers. Docs & TBs included.
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