A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.
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Updated
Jan 4, 2020 - Verilog
A trivial riscv cpu with tomasulo algorithm implemented in Verilog HDL. Support out-of-order execution and pipline and can run in FPGA with at 100MHz.
Simulation of the Tomasulo algorithm using python and verilog.Python code has been included to simulate dynamic instruction scheduling.This project was done as the part of Computer Architecture course.
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