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veryl

Here are 2 public repositories matching this topic...

YSawc / uarty

Uart implementation for FPGA with veryl.

rust verilog systemverilog veryl

Updated Jun 27, 2024

YSawc / embassyFc2

developing NES on FPGA project.

rust nes hdl embassy family-computer famicon veryl

Updated Jul 29, 2024
Rust

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