vhdl-testbench
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VHDL implementation of Up counter.
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Dec 6, 2020 - VHDL
A Time-Based Clap Lock Mechanism in Lower-Level Machine Implementation. Created by 4-Member Team VHDL Project in CPE 016 — Introduction to VHDL | Implemented in HDL 2008.
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Dec 8, 2020 - VHDL
Final Project - Reti Logiche. Politecnico di Milano, A.A. 2019-2020
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Dec 22, 2020 - VHDL
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Feb 22, 2021 - VHDL
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Jul 18, 2021 - VHDL
all projects of vhdl course of university
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Sep 19, 2021 - VHDL
A resource-friendly VHDL model for large memory simulations
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Sep 26, 2021 - VHDL
Aqui eu tento documentar o que fiz enquanto estudava a linguagem de descrição de hardware VHDL. Pretendo aumentar a lista e categorizar também.
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Jan 9, 2022 - VHDL
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Mar 9, 2022 - VHDL
VHDL course at Brno University of Technology
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May 13, 2022 - VHDL
Simple VHDL examples using ghdl as compiler and wave generating
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Jun 21, 2022 - VHDL
implementation of 4-bit BCD up/down counter. The counter work as follows: ● If input X = 0, the counter counts up. Otherwise, it counts down. ● If counting up, the counter’s value should be: 0000, 0001, 0010... ● If counting down: 0010, 0001, 0000...
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Oct 7, 2022 - VHDL
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Oct 22, 2022 - VHDL
The PWM (Pulse Width Modulation) Generator creates a PWM signal to control PWM-driven devices. It allows configurable clock and PWM frequencies via generics. The duty cycle, input as a 7-bit signal, adjusts the proportion of time the signal is high.
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Jul 4, 2024 - VHDL
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