VHDL 2008/93/87 simulator

An abstraction library for interfacing EDA tools

Repurposing existing HDL tools to help writing better code

SPI master and SPI slave for FPGA written in VHDL

A Python package to use FPGA development tools programmatically.

Simple UART controller for FPGA written in VHDL

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

A JSON library implemented in VHDL.

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.

Scripts to build and use docker images including GHDL

Trying to verify Verilog/VHDL designs with formal methods and tools

Virtual development board for HDL design

cryptography ip-cores in vhdl / verilog

IP Core Library - Published and maintained by the Open Source VHDL Group

✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.

Library of reusable VHDL components

HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model