Design of High-Level Synthesis of Xilinx FFT IP core via FFT library
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Updated
Jul 17, 2023 - Tcl
Design of High-Level Synthesis of Xilinx FFT IP core via FFT library
This is a design for the test of AXI_HP on PYNQ-Z1 (as well as Z2, maybe)
PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx
N-bit Full Adders implementation in VHDL
Zynq Book Tutorials adapted for the Digilent PYNQ-Z1
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