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Harry Wentlandalexdeucher
Harry Wentland
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alexdeucher
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drm/amd/display: Drop DCN1_01 guards
[WHY] These were only needed for bringup. They're not needed anymore. Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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-51
lines changed

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‎drivers/gpu/drm/amd/display/Kconfig‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,6 @@ config DRM_AMD_DC
55
bool "AMD DC - Enable new display engine"
66
default y
77
select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
8-
select DRM_AMD_DC_DCN1_01 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS)
98
help
109
Choose this option if you want to use the new display engine
1110
support for AMDGPU. This adds required support for Vega and
@@ -16,11 +15,6 @@ config DRM_AMD_DC_DCN1_0
1615
help
1716
RV family support for display engine
1817

19-
config DRM_AMD_DC_DCN1_01
20-
def_bool n
21-
help
22-
RV2 family for display engine
23-
2418
config DEBUG_KERNEL_DC
2519
bool "Enable kgdb break in DC"
2620
depends on DRM_AMD_DC

‎drivers/gpu/drm/amd/display/dc/bios/command_table_helper2.c‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -57,11 +57,6 @@ bool dal_bios_parser_init_cmd_tbl_helper2(
5757
return true;
5858
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
5959
case DCN_VERSION_1_0:
60-
*h = dal_cmd_tbl_helper_dce112_get_table2();
61-
return true;
62-
#endif
63-
64-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
6560
case DCN_VERSION_1_01:
6661
*h = dal_cmd_tbl_helper_dce112_get_table2();
6762
return true;

‎drivers/gpu/drm/amd/display/dc/core/dc_resource.c‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -93,10 +93,8 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
9393
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
9494
case FAMILY_RV:
9595
dc_version = DCN_VERSION_1_0;
96-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
9796
if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev))
9897
dc_version = DCN_VERSION_1_01;
99-
#endif
10098
break;
10199
#endif
102100
default:
@@ -147,9 +145,7 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc,
147145

148146
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
149147
case DCN_VERSION_1_0:
150-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
151148
case DCN_VERSION_1_01:
152-
#endif
153149
res_pool = dcn10_create_resource_pool(init_data, dc);
154150
break;
155151
#endif

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -927,9 +927,7 @@ void hubbub1_construct(struct hubbub *hubbub,
927927
hubbub1->masks = hubbub_mask;
928928

929929
hubbub1->debug_test_index_pstate = 0x7;
930-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
931930
if (ctx->dce_version == DCN_VERSION_1_01)
932931
hubbub1->debug_test_index_pstate = 0xB;
933-
#endif
934932
}
935933

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c‎

Lines changed: 0 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -152,9 +152,7 @@ enum dcn10_clk_src_array_id {
152152
DCN10_CLK_SRC_PLL2,
153153
DCN10_CLK_SRC_PLL3,
154154
DCN10_CLK_SRC_TOTAL,
155-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
156155
DCN101_CLK_SRC_TOTAL = DCN10_CLK_SRC_PLL3
157-
#endif
158156
};
159157

160158
/* begin *********************
@@ -522,7 +520,6 @@ static const struct resource_caps res_cap = {
522520
.num_ddc = 4,
523521
};
524522

525-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
526523
static const struct resource_caps rv2_res_cap = {
527524
.num_timing_generator = 3,
528525
.num_opp = 3,
@@ -532,7 +529,6 @@ static const struct resource_caps rv2_res_cap = {
532529
.num_pll = 3,
533530
.num_ddc = 3,
534531
};
535-
#endif
536532

537533
static const struct dc_plane_cap plane_cap = {
538534
.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
@@ -1270,11 +1266,9 @@ static bool construct(
12701266

12711267
ctx->dc_bios->regs = &bios_regs;
12721268

1273-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
12741269
if (ctx->dce_version == DCN_VERSION_1_01)
12751270
pool->base.res_cap = &rv2_res_cap;
12761271
else
1277-
#endif
12781272
pool->base.res_cap = &res_cap;
12791273
pool->base.funcs = &dcn10_res_pool_funcs;
12801274

@@ -1291,10 +1285,8 @@ static bool construct(
12911285
/* max pipe num for ASIC before check pipe fuses */
12921286
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
12931287

1294-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
12951288
if (dc->ctx->dce_version == DCN_VERSION_1_01)
12961289
pool->base.pipe_count = 3;
1297-
#endif
12981290
dc->caps.max_video_width = 3840;
12991291
dc->caps.max_downscale_ratio = 200;
13001292
dc->caps.i2c_speed_in_khz = 100;
@@ -1327,26 +1319,17 @@ static bool construct(
13271319
CLOCK_SOURCE_COMBO_PHY_PLL2,
13281320
&clk_src_regs[2], false);
13291321

1330-
#ifdef CONFIG_DRM_AMD_DC_DCN1_01
13311322
if (dc->ctx->dce_version == DCN_VERSION_1_0) {
13321323
pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
13331324
dcn10_clock_source_create(ctx, ctx->dc_bios,
13341325
CLOCK_SOURCE_COMBO_PHY_PLL3,
13351326
&clk_src_regs[3], false);
13361327
}
1337-
#else
1338-
pool->base.clock_sources[DCN10_CLK_SRC_PLL3] =
1339-
dcn10_clock_source_create(ctx, ctx->dc_bios,
1340-
CLOCK_SOURCE_COMBO_PHY_PLL3,
1341-
&clk_src_regs[3], false);
1342-
#endif
13431328

13441329
pool->base.clk_src_count = DCN10_CLK_SRC_TOTAL;
13451330

1346-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
13471331
if (dc->ctx->dce_version == DCN_VERSION_1_01)
13481332
pool->base.clk_src_count = DCN101_CLK_SRC_TOTAL;
1349-
#endif
13501333

13511334
pool->base.dp_clock_source =
13521335
dcn10_clock_source_create(ctx, ctx->dc_bios,
@@ -1386,7 +1369,6 @@ static bool construct(
13861369
memcpy(dc->dcn_ip, &dcn10_ip_defaults, sizeof(dcn10_ip_defaults));
13871370
memcpy(dc->dcn_soc, &dcn10_soc_defaults, sizeof(dcn10_soc_defaults));
13881371

1389-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
13901372
if (dc->ctx->dce_version == DCN_VERSION_1_01) {
13911373
struct dcn_soc_bounding_box *dcn_soc = dc->dcn_soc;
13921374
struct dcn_ip_params *dcn_ip = dc->dcn_ip;
@@ -1397,7 +1379,6 @@ static bool construct(
13971379
dcn_soc->dram_clock_change_latency = 23;
13981380
dcn_ip->max_num_dpp = 3;
13991381
}
1400-
#endif
14011382
if (ASICREV_IS_RV1_F0(dc->ctx->asic_id.hw_internal_rev)) {
14021383
dc->dcn_soc->urgent_latency = 3;
14031384
dc->debug.disable_dmcu = true;

‎drivers/gpu/drm/amd/display/dc/gpio/hw_factory.c‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -84,10 +84,6 @@ bool dal_hw_factory_init(
8484
return true;
8585
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
8686
case DCN_VERSION_1_0:
87-
dal_hw_factory_dcn10_init(factory);
88-
return true;
89-
#endif
90-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
9187
case DCN_VERSION_1_01:
9288
dal_hw_factory_dcn10_init(factory);
9389
return true;

‎drivers/gpu/drm/amd/display/dc/gpio/hw_translate.c‎

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -84,11 +84,6 @@ bool dal_hw_translate_init(
8484
dal_hw_translate_dcn10_init(translate);
8585
return true;
8686
#endif
87-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
88-
case DCN_VERSION_1_01:
89-
dal_hw_translate_dcn10_init(translate);
90-
return true;
91-
#endif
9287

9388
default:
9489
BREAK_TO_DEBUGGER();

‎drivers/gpu/drm/amd/display/include/dal_asic_id.h‎

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -131,22 +131,18 @@
131131
#define INTERNAL_REV_RAVEN_A0 0x00 /* First spin of Raven */
132132
#define RAVEN_A0 0x01
133133
#define RAVEN_B0 0x21
134-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
135134
/* DCN1_01 */
136135
#define PICASSO_A0 0x41
137136
#define RAVEN2_A0 0x81
138-
#endif
139137
#define RAVEN1_F0 0xF0
140138
#define RAVEN_UNKNOWN 0xFF
141139

142140
#define ASIC_REV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
143141
#define RAVEN1_F0 0xF0
144142
#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
145143

146-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
147144
#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
148145
#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0))
149-
#endif /* DCN1_01 */
150146

151147
#define FAMILY_RV 142 /* DCN 1*/
152148

‎drivers/gpu/drm/amd/display/include/dal_types.h‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,9 +45,7 @@ enum dce_version {
4545
DCE_VERSION_12_1,
4646
DCE_VERSION_MAX,
4747
DCN_VERSION_1_0,
48-
#if defined(CONFIG_DRM_AMD_DC_DCN1_01)
4948
DCN_VERSION_1_01,
50-
#endif /* DCN1_01 */
5149
DCN_VERSION_MAX
5250
};
5351

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