Project as part of the class HW-1, 7th semester, in ECE Aristotle University of Thessaloniki.
Design and verification of a simple RISC-V processor.
Made in Verilog.
Included are the .v files, project description and final report.
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tsarnadelis/RISC-V
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Project as part of the class HW-1, 7th semester, in ECE Aristotle University of Thessaloniki.
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