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Swap two arguments to resolve bug #941

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merged 1 commit into from
Aug 30, 2021
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zslwyuan
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@zslwyuan zslwyuan commented Aug 12, 2021

Related issue: N/A

Type of change: bug fix

Impact: other

Release Notes
The string of path for "-ip-vivado-tcls" could be empty ("")
For example, run "make SUB_PROJECT=arty bitstream" will get errors due to the argument parsing in prologue.tcl since there is no generated file like "XXX.vivado.tcl " in the working directory.
Swaping the two arguments can resolve bug.

**Related issue**: N/A

**Type of change**: bug fix

**Impact**: other

**Release Notes**
The string of path for "-ip-vivado-tcls" could be empty ("")
For example, run "make SUB_PROJECT=arty bitstream" will get errors due the argument parsing in [prologue.tcl](https://github.com/sifive/fpga-shells/blob/d4b3878e4f5cf5c4621dbfe9b0bda1ed0dd3b995/xilinx/common/tcl/prologue.tcl)
Swaping the two arguments can resolve bug.
@abejgonzalez
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@jamesdunn Can you confirm this issue? How did this work in the past?

@zslwyuan
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zslwyuan commented Aug 23, 2021

For your information, the version of our Vivado tools is 2021.1

@abejgonzalez
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I don't see this error on my end (running make SUB_PROJECT=arty bitstream) and I am running Vivado 2020.2. I've also confirmed that arg parsing is correct. Can you post the specific error/log?

@zslwyuan
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zslwyuan commented Aug 25, 2021

Running with RISCV=/home/tmpServer/Softwares/chipyard/riscv-tools-install
mkdir -p /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig
cp -f /home/tmpServer/Softwares/chipyard/generators/rocket-chip/src/main/resources/vsrc/EICG_wrapper.v /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig
echo "/home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/EICG_wrapper.v" >> /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/sim_files.f;
cp -f /home/tmpServer/Softwares/chipyard/generators/testchipip/src/main/resources/testchipip/bootrom/bootrom.rv64.img /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/bootrom.rv64.img
cp -f /home/tmpServer/Softwares/chipyard/generators/testchipip/src/main/resources/testchipip/bootrom/bootrom.rv32.img /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/bootrom.rv32.img
mkdir -p /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig
cd /home/tmpServer/Softwares/chipyard && java -Xmx8G -Xss8M -XX:MaxPermSize=256M -Djava.io.tmpdir=/home/tmpServer/Softwares/chipyard/.java_tmp -jar /home/tmpServer/Softwares/chipyard/generators/rocket-chip/sbt-launch.jar -Dsbt.sourcemode=true -Dsbt.workspace=/home/tmpServer/Softwares/chipyard/tools  ";project fpga_platforms; runMain chipyard.Generator  --target-dir /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig --name chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig --top-module chipyard.fpga.arty.ArtyFPGATestHarness --legacy-configs chipyard.fpga.arty:TinyRocketArtyConfig"
OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0
[info] welcome to sbt 1.4.9 (Private Build Java 1.8.0_292)
[info] loading global plugins from /home/tmpServer/.sbt/1.0/plugins
[info] loading settings for project chipyard-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/project
[info] loading settings for project chipyardRoot from build.sbt ...
[info] loading settings for project hardfloat from build.sbt ...
[info] loading settings for project rocketConfig from build.sbt ...
[info] loading settings for project firrtl_interpreter from build.sbt ...
[info] loading settings for project treadle from build.sbt ...
[info] loading settings for project chisel_testers from build.sbt ...
[info] loading settings for project testchipip from build.sbt ...
[info] loading settings for project icenet from build.sbt ...
[info] loading settings for project hwacha from build.sbt ...
[info] loading settings for project boom from build.sbt ...
[info] loading settings for project cva6 from build.sbt ...
[info] loading settings for project sodor from build.sbt ...
[info] loading settings for project gemmini from build.sbt ...
[info] loading settings for project mdf from build.sbt ...
[info] loading settings for project barstoolsMacros from build.sbt ...
[info] loading settings for project sim-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/sims/firesim/sim/project
[info] loading settings for project firesim from build.sbt ...
[info] loading settings for project targetutils from build.sbt ...
[info] loading settings for project midas from build.sbt ...
[info] loading settings for project chisel3-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/tools/chisel3/project
[info] loading settings for project chisel from build.sbt ...
[info] loading settings for project firrtl-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/tools/firrtl/project
[info] loading settings for project firrtl from build.sbt ...
[info] resolving key references (55417 settings) ...
[info] set current project to chipyardRoot (in build file:/home/tmpServer/Softwares/chipyard/)
[info] set current project to fpga_platforms (in build file:/home/tmpServer/Softwares/chipyard/)
[info] compiling 1 Scala source to /home/tmpServer/Softwares/chipyard/tools/chisel3/plugin/target/scala-2.12.12/classes ...
[info] compiling 60 Scala sources to /home/tmpServer/Softwares/chipyard/tools/chisel3/target/scala-2.12/classes ...
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/ChiselExecutionOptions.scala:21:44: trait ComposableOptions in package firrtl is deprecated (since FIRRTL 1.2): Use firrtl.options.HasScoptOptions and/or library/transform registration
[warn]                                  ) extends ComposableOptions {
[warn]                                            ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/ChiselExecutionOptions.scala:30:9: class ExecutionOptionsManager in package firrtl is deprecated (since FIRRTL 1.2): Use new FirrtlStage infrastructure
[warn]   self: ExecutionOptionsManager =>
[warn]         ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/Driver.scala:41:43: trait BackendCompilationUtilities in package util is deprecated (since FIRRTL 1.3): use object BackendCompilationUtilities
[warn] trait BackendCompilationUtilities extends FirrtlBackendCompilationUtilities {
[warn]                                           ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/Driver.scala:49:30: class ExecutionOptionsManager in package firrtl is deprecated (since FIRRTL 1.2): Use new FirrtlStage infrastructure
[warn]     val optionsManager = new ExecutionOptionsManager("chisel3") with HasChiselExecutionOptions with HasFirrtlOptions {
[warn]                              ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/Driver.scala:49:101: trait HasFirrtlOptions in package firrtl is deprecated (since FIRRTL 1.2): Specify command line arguments in an Annotation mixing in HasScoptOptions
[warn]     val optionsManager = new ExecutionOptionsManager("chisel3") with HasChiselExecutionOptions with HasFirrtlOptions {
[warn]                                                                                                     ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/Driver.scala:50:23: class CommonOptions in package firrtl is deprecated (since FIRRTL 1.2): Use a FirrtlOptionsView, LoggerOptionsView, or construct your own view of an AnnotationSeq
[warn]       commonOptions = CommonOptions(topName = prefix, targetDirName = dir.getAbsolutePath)
[warn]                       ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/Driver.scala:51:23: class FirrtlExecutionOptions in package firrtl is deprecated (since FIRRTL 1.2): Use a FirrtlOptionsView or construct your own view of an AnnotationSeq
[warn]       firrtlOptions = FirrtlExecutionOptions(compilerName = "verilog")
[warn]                       ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/Driver.scala:54:12: object Driver in package firrtl is deprecated (since FIRRTL 1.2): Use firrtl.stage.FirrtlStage
[warn]     firrtl.Driver.execute(optionsManager) match {
[warn]            ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala:14:27: class CircuitForm in package firrtl is deprecated (since FIRRTL 1.3): Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre
[warn]   override def inputForm: CircuitForm = ChirrtlForm
[warn]                           ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala:14:41: object ChirrtlForm in package firrtl is deprecated (since FIRRTL 1.3): Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre
[warn]   override def inputForm: CircuitForm = ChirrtlForm
[warn]                                         ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala:15:28: class CircuitForm in package firrtl is deprecated (since FIRRTL 1.3): Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre
[warn]   override def outputForm: CircuitForm = ChirrtlForm
[warn]                            ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala:15:42: object ChirrtlForm in package firrtl is deprecated (since FIRRTL 1.3): Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre
[warn]   override def outputForm: CircuitForm = ChirrtlForm
[warn]                                          ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/compatibility.scala:268:24: method io in class BlackBox is deprecated (since Chisel 3.4): Removed for causing issues in Scala 2.12+. You remain free to define io Bundles in your BlackBoxes, but you cannot rely on an io field in every BlackBox. For more information, see: https://github.com/freechipsproject/chisel3/pull/1550.
[warn]         _bindIoInPlace(io)
[warn]                        ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/compatibility.scala:326:36: method io in class LegacyModule is deprecated (since Chisel 3.4): Removed for causing issues in Scala 2.12+. You remain free to define io Bundles in your Modules, but you cannot rely on an io field in every Module. For more information, see: https://github.com/freechipsproject/chisel3/pull/1550.
[warn]       if (!_compatIoPortBound() && io != null) {
[warn]                                    ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/compatibility.scala:327:24: method io in class LegacyModule is deprecated (since Chisel 3.4): Removed for causing issues in Scala 2.12+. You remain free to define io Bundles in your Modules, but you cannot rely on an io field in every Module. For more information, see: https://github.com/freechipsproject/chisel3/pull/1550.
[warn]         _bindIoInPlace(io)
[warn]                        ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/compatibility.scala:398:50: trait BackendCompilationUtilities in package util is deprecated (since FIRRTL 1.3): use object BackendCompilationUtilities
[warn]   type BackendCompilationUtilities = firrtl.util.BackendCompilationUtilities
[warn]                                                  ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/compatibility.scala:491:29: object unless in package util is deprecated (since 3.2): The unless conditional is deprecated, use when(!condition){...} instead
[warn]   val unless = chisel3.util.unless
[warn]                             ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/stage/package.scala:28:70: trait ChiselExecutionResult in package chisel3 is deprecated (since Chisel3 3.4): This will be removed in Chisel 3.5
[warn]   private[chisel3] implicit object ChiselExecutionResultView extends OptionsView[ChiselExecutionResult] {
[warn]                                                                      ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/stage/package.scala:30:39: trait ChiselExecutionResult in package chisel3 is deprecated (since Chisel3 3.4): This will be removed in Chisel 3.5
[warn]     def view(options: AnnotationSeq): ChiselExecutionResult = {
[warn]                                       ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/stage/package.scala:44:61: method firrtlResultView in object DriverCompatibility is deprecated (since 1.2): FirrtlExecutionResult is deprecated as part of the Stage/Phase refactor. Migrate to FirrtlStage.
[warn]       val fResult = firrtl.stage.phases.DriverCompatibility.firrtlResultView(options)
[warn]                                                             ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/stage/package.scala:47:36: class ChiselExecutionFailure in package chisel3 is deprecated (since Chisel 3.4): This will be removed in Chisel 3.5
[warn]         case (None, _)          => ChiselExecutionFailure("Failed to elaborate Chisel circuit")
[warn]                                    ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/stage/package.scala:48:36: class ChiselExecutionFailure in package chisel3 is deprecated (since Chisel 3.4): This will be removed in Chisel 3.5
[warn]         case (Some(_), None)    => ChiselExecutionFailure("Failed to convert Chisel circuit to FIRRTL")
[warn]                                    ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/stage/package.scala:49:36: class ChiselExecutionSuccess in package chisel3 is deprecated (since Chisel 3.4): This will be removed in Chisel 3.5
[warn]         case (Some(a), Some(b)) => ChiselExecutionSuccess( Some(a), b, Some(fResult))
[warn]                                    ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala:114:14: class ExecutionOptionsManager in package firrtl is deprecated (since FIRRTL 1.2): Use new FirrtlStage infrastructure
[warn]     manager: ExecutionOptionsManager with HasChiselExecutionOptions with HasFirrtlOptions)
[warn]              ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala:113:31: class ExecutionOptionsManager in package firrtl is deprecated (since FIRRTL 1.2): Use new FirrtlStage infrastructure
[warn]   private[chisel3] case class OptionsManagerAnnotation(
[warn]                               ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala:131:22: class ExecutionOptionsManager in package firrtl is deprecated (since FIRRTL 1.2): Use new FirrtlStage infrastructure
[warn]         .collectFirst{ case OptionsManagerAnnotation(a) => a }
[warn]                      ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala:159:56: class AddImplicitOutputFile in object DriverCompatibility is deprecated (since 1.2): AddImplicitOutputFile should only be used to build Driver compatibility wrappers. Switch to Stage.
[warn]       Seq( new firrtl.stage.phases.DriverCompatibility.AddImplicitOutputFile,
[warn]                                                        ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/stage/phases/DriverCompatibility.scala:160:56: class AddImplicitEmitter in object DriverCompatibility is deprecated (since 1.2): AddImplicitEmitter should only be used to build Driver compatibility wrappers. Switch to Stage.
[warn]            new firrtl.stage.phases.DriverCompatibility.AddImplicitEmitter )
[warn]                                                        ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala:127:18: class CircuitForm in package firrtl is deprecated (since FIRRTL 1.3): Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre
[warn]   def inputForm: CircuitForm  = LowForm
[warn]                  ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala:127:33: object LowForm in package firrtl is deprecated (since FIRRTL 1.3): Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre
[warn]   def inputForm: CircuitForm  = LowForm
[warn]                                 ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala:128:19: class CircuitForm in package firrtl is deprecated (since FIRRTL 1.3): Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre
[warn]   def outputForm: CircuitForm = LowForm
[warn]                   ^
[warn] /home/tmpServer/Softwares/chipyard/tools/chisel3/src/main/scala/chisel3/util/experimental/LoadMemoryTransform.scala:128:33: object LowForm in package firrtl is deprecated (since FIRRTL 1.3): Mix-in the DependencyAPIMigration trait into your Transform and specify its Dependency API dependencies. See: https://bit.ly/2Voppre
[warn]   def outputForm: CircuitForm = LowForm
[warn]                                 ^
[warn] 32 warnings found
[info] compiling 1 Scala source to /home/tmpServer/Softwares/chipyard/generators/rocket-chip/hardfloat/target/scala-2.12/classes ...
[info] compiling 75 Scala sources to /home/tmpServer/Softwares/chipyard/generators/rocket-chip/src/target/scala-2.12/classes ...
[warn] there were 1459 feature warnings; re-run with -feature for details
[warn] one warning found
[info] compiling 10 Scala sources to /home/tmpServer/Softwares/chipyard/generators/sha3/target/scala-2.12/classes ...
[info] compiling 9 Scala sources to /home/tmpServer/Softwares/chipyard/generators/sifive-cache/target/scala-2.12/classes ...
[info] compiling 2 Scala sources to /home/tmpServer/Softwares/chipyard/generators/riscv-sodor/target/scala-2.12/classes ...
[info] compiling 3 Scala sources to /home/tmpServer/Softwares/chipyard/tools/rocket-dsp-utils/src/target/scala-2.12/classes ...
[info] compiling 27 Scala sources to /home/tmpServer/Softwares/chipyard/generators/sifive-blocks/target/scala-2.12/classes ...
[info] compiling 53 Scala sources to /home/tmpServer/Softwares/chipyard/generators/hwacha/target/scala-2.12/classes ...
[warn] /home/tmpServer/Softwares/chipyard/tools/rocket-dsp-utils/src/main/scala/freechips/rocketchip/jtag2mm/JtagToMaster.scala:133:11: method apply in object TLClientPortParameters is deprecated: Use TLMasterPortParameters.v1 instead of TLClientPortParameters
[warn]       Seq(TLClientPortParameters(Seq(TLClientParameters(name = "JTAGToMasterOut", sourceId = IdRange(0, 4)))))
[warn]           ^
[warn] /home/tmpServer/Softwares/chipyard/tools/rocket-dsp-utils/src/main/scala/freechips/rocketchip/jtag2mm/JtagToMaster.scala:133:38: method apply in object TLClientParameters is deprecated: Use TLMasterParameters.v1 instead of TLClientParameters
[warn]       Seq(TLClientPortParameters(Seq(TLClientParameters(name = "JTAGToMasterOut", sourceId = IdRange(0, 4)))))
[warn]                                      ^
[warn] /home/tmpServer/Softwares/chipyard/tools/rocket-dsp-utils/src/main/scala/freechips/rocketchip/jtag2mm/JtagToMaster.scala:468:23: method apply in object TLManagerParameters is deprecated: Use TLSlaveParameters.v1 instead of TLManagerParameters
[warn]   val managerParams = TLManagerParameters(
[warn]                       ^
[warn] three warnings found
[warn] /home/tmpServer/Softwares/chipyard/generators/sifive-blocks/src/main/scala/devices/gpio/GPIO.scala:293:44: match may not be exhaustive.
[warn] It would fail on the following input: CreditedCrossing(_, _)
[warn]       gpioClockDomainWrapper.clockNode := (controlXType match {
[warn]                                            ^
[warn] /home/tmpServer/Softwares/chipyard/generators/sifive-blocks/src/main/scala/devices/gpio/GPIO.scala:310:6: match may not be exhaustive.
[warn] It would fail on the following input: CreditedCrossing(_, _)
[warn]     (intXType match {
[warn]      ^
[warn] /home/tmpServer/Softwares/chipyard/generators/sifive-blocks/src/main/scala/devices/i2c/I2C.scala:608:43: match may not be exhaustive.
[warn] It would fail on the following input: CreditedCrossing(_, _)
[warn]       i2cClockDomainWrapper.clockNode := (controlXType match {
[warn]                                           ^
[warn] /home/tmpServer/Softwares/chipyard/generators/sifive-blocks/src/main/scala/devices/i2c/I2C.scala:625:6: match may not be exhaustive.
[warn] It would fail on the following input: CreditedCrossing(_, _)
[warn]     (intXType match {
[warn]      ^
[warn] /home/tmpServer/Softwares/chipyard/generators/sifive-blocks/src/main/scala/devices/pwm/PWM.scala:146:43: match may not be exhaustive.
[warn] It would fail on the following input: CreditedCrossing(_, _)
[warn]       pwmClockDomainWrapper.clockNode := (controlXType match {
[warn]                                           ^
[warn] /home/tmpServer/Softwares/chipyard/generators/sifive-blocks/src/main/scala/devices/pwm/PWM.scala:163:6: match may not be exhaustive.
[warn] It would fail on the following input: CreditedCrossing(_, _)
[warn]     (intXType match {
[warn]      ^
[warn] /home/tmpServer/Softwares/chipyard/generators/sifive-blocks/src/main/scala/devices/stream/PseudoStream.scala:119:46: match may not be exhaustive.
[warn] It would fail on the following input: CreditedCrossing(_, _)
[warn]       streamClockDomainWrapper.clockNode := (controlXType match {
[warn]                                              ^
[warn] there were 513 feature warnings; re-run with -feature for details
[warn] one warning found
[warn] there were 217 feature warnings; re-run with -feature for details
[warn] one warning found
[warn] there were 467 feature warnings; re-run with -feature for details
[warn] 8 warnings found
[info] compiling 2 Scala sources to /home/tmpServer/Softwares/chipyard/generators/testchipip/target/scala-2.12/classes ...
[info] compiling 4 Scala sources to /home/tmpServer/Softwares/chipyard/fpga/fpga-shells/target/scala-2.12/classes ...
[warn] there were 11 feature warnings; re-run with -feature for details
[warn] one warning found
[info] compiling 1 Scala source to /home/tmpServer/Softwares/chipyard/generators/icenet/target/scala-2.12/classes ...
[info] compiling 8 Scala sources to /home/tmpServer/Softwares/chipyard/generators/gemmini/target/scala-2.12/classes ...
[info] compiling 8 Scala sources to /home/tmpServer/Softwares/chipyard/generators/boom/target/scala-2.12/classes ...
[warn] there were 83 feature warnings; re-run with -feature for details
[warn] one warning found
[warn] there were 60 feature warnings; re-run with -feature for details
[warn] one warning found
[warn] /home/tmpServer/Softwares/chipyard/generators/hwacha/src/main/scala/vmu.scala:139:9: method io is deprecated (since Chisel 3.4): Removed for causing issues in Scala 2.12+. You remain free to define io Bundles in your Modules, but you cannot rely on an io field in every Module. For more information, see: https://github.com/freechipsproject/chisel3/pull/1550.
[warn]   agent.io.op.bits := op
[warn]         ^
[warn] /home/tmpServer/Softwares/chipyard/generators/hwacha/src/main/scala/vmu.scala:140:9: method io is deprecated (since Chisel 3.4): Removed for causing issues in Scala 2.12+. You remain free to define io Bundles in your Modules, but you cannot rely on an io field in every Module. For more information, see: https://github.com/freechipsproject/chisel3/pull/1550.
[warn]   agent.io.op.valid := opq.io.deq.valid
[warn]         ^
[warn] /home/tmpServer/Softwares/chipyard/generators/hwacha/src/main/scala/vmu.scala:141:29: method io is deprecated (since Chisel 3.4): Removed for causing issues in Scala 2.12+. You remain free to define io Bundles in your Modules, but you cannot rely on an io field in every Module. For more information, see: https://github.com/freechipsproject/chisel3/pull/1550.
[warn]   opq.io.deq.ready := agent.io.op.ready
[warn]                             ^
[warn] /home/tmpServer/Softwares/chipyard/generators/hwacha/src/main/scala/vmu.scala:142:20: method io is deprecated (since Chisel 3.4): Removed for causing issues in Scala 2.12+. You remain free to define io Bundles in your Modules, but you cannot rely on an io field in every Module. For more information, see: https://github.com/freechipsproject/chisel3/pull/1550.
[warn]   io.aret := agent.io.aret
[warn]                    ^
[warn] /home/tmpServer/Softwares/chipyard/generators/hwacha/src/main/scala/vmu.scala:145:11: method io is deprecated (since Chisel 3.4): Removed for causing issues in Scala 2.12+. You remain free to define io Bundles in your Modules, but you cannot rely on an io field in every Module. For more information, see: https://github.com/freechipsproject/chisel3/pull/1550.
[warn]     agent.io.span(io.abox(1), io.pbox(1)), io.abox(2))
[warn]           ^
[warn] /home/tmpServer/Softwares/chipyard/generators/hwacha/src/main/scala/vmu.scala:146:19: method io is deprecated (since Chisel 3.4): Removed for causing issues in Scala 2.12+. You remain free to define io Bundles in your Modules, but you cannot rely on an io field in every Module. For more information, see: https://github.com/freechipsproject/chisel3/pull/1550.
[warn]   issue zip agent.io.issue map {case(s,d) => s <> d}
[warn]                   ^
[warn] there were 390 feature warnings; re-run with -feature for details
[warn] one warning found
[warn] there were 3031 feature warnings; re-run with -feature for details
[warn] 7 warnings found
[warn] there were 1079 feature warnings; re-run with -feature for details
[warn] one warning found
[info] running chipyard.Generator --target-dir /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig --name chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig --top-module chipyard.fpga.arty.ArtyFPGATestHarness --legacy-configs chipyard.fpga.arty:TinyRocketArtyConfig
Elaborating design...
Interrupt map (1 harts 1 interrupts):
  [1, 1] => uart_0

<stdout>: Warning (simple_bus_reg): Node /soc/subsystem_pbus_clock missing or empty reg/ranges property
Clock subsystem_pbus_0: using diplomatically specified frequency of 100.0.
/dts-v1/;

/ {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "freechips,rocketchip-unknown-dev";
        model = "freechips,rocketchip-unknown";
        L21: aliases {
                serial0 = &L16;
        };
        L20: cpus {
                #address-cells = <1>;
                #size-cells = <0>;
                L5: cpu@0 {
                        clock-frequency = <0>;
                        compatible = "sifive,rocket0", "riscv";
                        device_type = "cpu";
                        hardware-exec-breakpoint-count = <2>;
                        i-cache-block-size = <64>;
                        i-cache-sets = <64>;
                        i-cache-size = <4096>;
                        reg = <0x0>;
                        riscv,isa = "rv32imac";
                        riscv,pmpgranularity = <4>;
                        riscv,pmpregions = <8>;
                        sifive,dtim = <&L4>;
                        status = "okay";
                        timebase-frequency = <32768>;
                        L2: interrupt-controller {
                                #interrupt-cells = <1>;
                                compatible = "riscv,cpu-intc";
                                interrupt-controller;
                        };
                };
        };
        L19: soc {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
                ranges;
                L15: boot-address-reg@4000 {
                        reg = <0x4000 0x1000>;
                        reg-names = "control";
                };
                L7: clint@2000000 {
                        compatible = "riscv,clint0";
                        interrupts-extended = <&L2 3 &L2 7>;
                        reg = <0x2000000 0x10000>;
                        reg-names = "control";
                };
                L8: debug-controller@0 {
                        compatible = "sifive,debug-013", "riscv,debug-013";
                        debug-attach = "jtag";
                        interrupts-extended = <&L2 65535>;
                        reg = <0x0 0x1000>;
                        reg-names = "control";
                };
                L4: dtim@80000000 {
                        compatible = "sifive,dtim0";
                        reg = <0x80000000 0x4000>;
                        reg-names = "mem";
                };
                L1: error-device@3000 {
                        compatible = "sifive,error0";
                        reg = <0x3000 0x1000>;
                };
                L6: interrupt-controller@c000000 {
                        #interrupt-cells = <1>;
                        compatible = "riscv,plic0";
                        interrupt-controller;
                        interrupts-extended = <&L2 11>;
                        reg = <0xc000000 0x4000000>;
                        reg-names = "control";
                        riscv,max-priority = <1>;
                        riscv,ndev = <1>;
                };
                L14: rom@10000 {
                        compatible = "sifive,rom0";
                        reg = <0x10000 0x10000>;
                        reg-names = "mem";
                };
                L16: serial@10013000 {
                        clocks = <&L0>;
                        compatible = "sifive,uart0";
                        interrupt-parent = <&L6>;
                        interrupts = <1>;
                        reg = <0x10013000 0x1000>;
                        reg-names = "control";
                };
                L0: subsystem_pbus_clock {
                        #clock-cells = <0>;
                        clock-frequency = <100000000>;
                        clock-output-names = "subsystem_pbus_clock";
                        compatible = "fixed-clock";
                };
                L17: tile-reset-ctrl@100000 {
                        reg = <0x100000 0x1000>;
                        reg-names = "control";
                };
        };
};

Generated Address Map
               0 -     1000 ARWX  debug-controller@0
            3000 -     4000 ARWX  error-device@3000
            4000 -     5000 ARW   boot-address-reg@4000
           10000 -    20000  R X  rom@10000
          100000 -   101000 ARW   tile-reset-ctrl@100000
         2000000 -  2010000 ARW   clint@2000000
         c000000 - 10000000 ARW   interrupt-controller@c000000
        10013000 - 10014000 ARW   serial@10013000
        80000000 - 80004000 ARWX  dtim@80000000


buildTopClockGenerator Frequency Summary
  Input Reference Frequency: 100.0 MHz
  Output clock implicit_clock, requested: 100.0 MHz, actual: 100.0 MHz (division of 1)
  Output clock subsystem_sbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1)
  Output clock subsystem_pbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1)
  Output clock subsystem_fbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1)
  Output clock subsystem_cbus_0, requested: 100.0 MHz, actual: 100.0 MHz (division of 1)
Done elaborating.
[success] Total time: 117 s (01:57), completed Aug 25, 2021 5:12:42 PM
cd /home/tmpServer/Softwares/chipyard && java -Xmx8G -Xss8M -XX:MaxPermSize=256M -Djava.io.tmpdir=/home/tmpServer/Softwares/chipyard/.java_tmp -jar /home/tmpServer/Softwares/chipyard/generators/rocket-chip/sbt-launch.jar -Dsbt.sourcemode=true -Dsbt.workspace=/home/tmpServer/Softwares/chipyard/tools  ";project tapeout; runMain barstools.tapeout.transforms.GenerateTopAndHarness -o /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.v -tho /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.v -i /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.fir --syn-top ChipTop --harness-top ArtyFPGATestHarness -faf /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.anno.json -tsaof /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.anno.json -tdf /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/firrtl_black_box_resource_files.top.f -tsf /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.fir -thaof /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.anno.json -hdf /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/firrtl_black_box_resource_files.harness.f -thf /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.fir --infer-rw --repl-seq-mem -c:ArtyFPGATestHarness:-o:/home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.mems.conf -thconf /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.mems.conf -td /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig -ll error" && touch /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/firrtl_black_box_resource_files.top.f /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/firrtl_black_box_resource_files.harness.f
OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0
[info] welcome to sbt 1.4.9 (Private Build Java 1.8.0_292)
[info] loading global plugins from /home/tmpServer/.sbt/1.0/plugins
[info] loading settings for project chipyard-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/project
[info] loading settings for project chipyardRoot from build.sbt ...
[info] loading settings for project hardfloat from build.sbt ...
[info] loading settings for project rocketConfig from build.sbt ...
[info] loading settings for project firrtl_interpreter from build.sbt ...
[info] loading settings for project treadle from build.sbt ...
[info] loading settings for project chisel_testers from build.sbt ...
[info] loading settings for project testchipip from build.sbt ...
[info] loading settings for project icenet from build.sbt ...
[info] loading settings for project hwacha from build.sbt ...
[info] loading settings for project boom from build.sbt ...
[info] loading settings for project cva6 from build.sbt ...
[info] loading settings for project sodor from build.sbt ...
[info] loading settings for project gemmini from build.sbt ...
[info] loading settings for project mdf from build.sbt ...
[info] loading settings for project barstoolsMacros from build.sbt ...
[info] loading settings for project sim-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/sims/firesim/sim/project
[info] loading settings for project firesim from build.sbt ...
[info] loading settings for project targetutils from build.sbt ...
[info] loading settings for project midas from build.sbt ...
[info] loading settings for project chisel3-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/tools/chisel3/project
[info] loading settings for project chisel from build.sbt ...
[info] loading settings for project firrtl-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/tools/firrtl/project
[info] loading settings for project firrtl from build.sbt ...
[info] resolving key references (55417 settings) ...
[info] set current project to chipyardRoot (in build file:/home/tmpServer/Softwares/chipyard/)
[info] set current project to tapeout (in build file:/home/tmpServer/Softwares/chipyard/)
[info] running barstools.tapeout.transforms.GenerateTopAndHarness -o /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.v -tho /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.v -i /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.fir --syn-top ChipTop --harness-top ArtyFPGATestHarness -faf /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.anno.json -tsaof /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.anno.json -tdf /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/firrtl_black_box_resource_files.top.f -tsf /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.fir -thaof /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.anno.json -hdf /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/firrtl_black_box_resource_files.harness.f -thf /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.fir --infer-rw --repl-seq-mem -c:ArtyFPGATestHarness:-o:/home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.mems.conf -thconf /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.mems.conf -td /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig -ll error
[success] Total time: 56 s, completed Aug 25, 2021 5:13:52 PM
awk '{print ;}' /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/sim_files.f /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/firrtl_black_box_resource_files.top.f /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/firrtl_black_box_resource_files.harness.f | sort -u | grep -v '.*\.\(svh\|h\)$' > /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/sim_files.common.f
cd /home/tmpServer/Softwares/chipyard && java -Xmx8G -Xss8M -XX:MaxPermSize=256M -Djava.io.tmpdir=/home/tmpServer/Softwares/chipyard/.java_tmp -jar /home/tmpServer/Softwares/chipyard/generators/rocket-chip/sbt-launch.jar -Dsbt.sourcemode=true -Dsbt.workspace=/home/tmpServer/Softwares/chipyard/tools  ";project barstoolsMacros; runMain barstools.macros.MacroCompiler -n /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.mems.conf -v /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.mems.v -f /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.mems.fir --mode synflops"
OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0
[info] welcome to sbt 1.4.9 (Private Build Java 1.8.0_292)
[info] loading global plugins from /home/tmpServer/.sbt/1.0/plugins
[info] loading settings for project chipyard-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/project
[info] loading settings for project chipyardRoot from build.sbt ...
[info] loading settings for project hardfloat from build.sbt ...
[info] loading settings for project rocketConfig from build.sbt ...
[info] loading settings for project firrtl_interpreter from build.sbt ...
[info] loading settings for project treadle from build.sbt ...
[info] loading settings for project chisel_testers from build.sbt ...
[info] loading settings for project testchipip from build.sbt ...
[info] loading settings for project icenet from build.sbt ...
[info] loading settings for project hwacha from build.sbt ...
[info] loading settings for project boom from build.sbt ...
[info] loading settings for project cva6 from build.sbt ...
[info] loading settings for project sodor from build.sbt ...
[info] loading settings for project gemmini from build.sbt ...
[info] loading settings for project mdf from build.sbt ...
[info] loading settings for project barstoolsMacros from build.sbt ...
[info] loading settings for project sim-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/sims/firesim/sim/project
[info] loading settings for project firesim from build.sbt ...
[info] loading settings for project targetutils from build.sbt ...
[info] loading settings for project midas from build.sbt ...
[info] loading settings for project chisel3-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/tools/chisel3/project
[info] loading settings for project chisel from build.sbt ...
[info] loading settings for project firrtl-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/tools/firrtl/project
[info] loading settings for project firrtl from build.sbt ...
[info] resolving key references (55417 settings) ...
[info] set current project to chipyardRoot (in build file:/home/tmpServer/Softwares/chipyard/)
[info] set current project to barstoolsMacros (in build file:/home/tmpServer/Softwares/chipyard/)
[info] running barstools.macros.MacroCompiler -n /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.mems.conf -v /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.mems.v -f /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.mems.fir --mode synflops
[success] Total time: 4 s, completed Aug 25, 2021 5:14:11 PM
cd /home/tmpServer/Softwares/chipyard && java -Xmx8G -Xss8M -XX:MaxPermSize=256M -Djava.io.tmpdir=/home/tmpServer/Softwares/chipyard/.java_tmp -jar /home/tmpServer/Softwares/chipyard/generators/rocket-chip/sbt-launch.jar -Dsbt.sourcemode=true -Dsbt.workspace=/home/tmpServer/Softwares/chipyard/tools  ";project barstoolsMacros; runMain barstools.macros.MacroCompiler  -n /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.mems.conf -v /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.mems.v -f /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.mems.fir --mode synflops"
OpenJDK 64-Bit Server VM warning: ignoring option MaxPermSize=256M; support was removed in 8.0
[info] welcome to sbt 1.4.9 (Private Build Java 1.8.0_292)
[info] loading global plugins from /home/tmpServer/.sbt/1.0/plugins
[info] loading settings for project chipyard-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/project
[info] loading settings for project chipyardRoot from build.sbt ...
[info] loading settings for project hardfloat from build.sbt ...
[info] loading settings for project rocketConfig from build.sbt ...
[info] loading settings for project firrtl_interpreter from build.sbt ...
[info] loading settings for project treadle from build.sbt ...
[info] loading settings for project chisel_testers from build.sbt ...
[info] loading settings for project testchipip from build.sbt ...
[info] loading settings for project icenet from build.sbt ...
[info] loading settings for project hwacha from build.sbt ...
[info] loading settings for project boom from build.sbt ...
[info] loading settings for project cva6 from build.sbt ...
[info] loading settings for project sodor from build.sbt ...
[info] loading settings for project gemmini from build.sbt ...
[info] loading settings for project mdf from build.sbt ...
[info] loading settings for project barstoolsMacros from build.sbt ...
[info] loading settings for project sim-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/sims/firesim/sim/project
[info] loading settings for project firesim from build.sbt ...
[info] loading settings for project targetutils from build.sbt ...
[info] loading settings for project midas from build.sbt ...
[info] loading settings for project chisel3-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/tools/chisel3/project
[info] loading settings for project chisel from build.sbt ...
[info] loading settings for project firrtl-build from plugins.sbt ...
[info] loading project definition from /home/tmpServer/Softwares/chipyard/tools/firrtl/project
[info] loading settings for project firrtl from build.sbt ...
[info] resolving key references (55417 settings) ...
[info] set current project to chipyardRoot (in build file:/home/tmpServer/Softwares/chipyard/)
[info] set current project to barstoolsMacros (in build file:/home/tmpServer/Softwares/chipyard/)
[info] running barstools.macros.MacroCompiler -n /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.mems.conf -v /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.mems.v -f /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.mems.fir --mode synflops
WARNING: Empty *.mems.conf file. No memories generated.
[success] Total time: 2 s, completed Aug 25, 2021 5:14:28 PM
echo "/home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.v" >> /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.vsrcs.f; echo "/home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.v" >> /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.vsrcs.f; echo "/home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.top.mems.v" >> /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.vsrcs.f; echo "/home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.harness.mems.v" >> /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.vsrcs.f; echo "/home/tmpServer/Softwares/chipyard/generators/sifive-blocks/vsrc/SRLatch.v" >> /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.vsrcs.f; echo "/home/tmpServer/Softwares/chipyard/fpga/fpga-shells/xilinx/common/vsrc/PowerOnResetFPGAOnly.v" >> /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.vsrcs.f;
cat /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/sim_files.common.f >> /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.vsrcs.f
cd /home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig; vivado \
        -nojournal -mode batch \
        -source /home/tmpServer/Softwares/chipyard/fpga/fpga-shells/xilinx/common/tcl/vivado.tcl \
        -tclargs \
                -top-module "ArtyFPGATestHarness" \
                -F "/home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig.vsrcs.f" \
                -ip-vivado-tcls "" \
                -board "arty"

****** Vivado v2020.1 (64-bit)
  **** SW Build 2902540 on Wed May 27 19:54:35 MDT 2020
  **** IP Build 2902112 on Wed May 27 22:43:36 MDT 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source /home/tmpServer/Softwares/chipyard/fpga/fpga-shells/xilinx/common/tcl/vivado.tcl
# set scriptdir [file dirname [info script]]
# source [file join $scriptdir "prologue.tcl"]
## set ip_vivado_tcls {}
## while {[llength $argv]} {
##   set argv [lassign $argv[set argv {}] flag]
##   switch -glob $flag {
##     -top-module {
##       set argv [lassign $argv[set argv {}] top]
##     }
##     -F {
##       # This should be a simple file format with one filepath per line
##       set argv [lassign $argv[set argv {}] vsrc_manifest]
##     }
##     -board {
##       set argv [lassign $argv[set argv {}] board]
##     }
##     -ip-vivado-tcls {
##       set argv [lassign $argv[set argv {}] ip_vivado_tcls]
##     }
##     -pre-impl-debug-tcl {
##       set argv [lassign $argv[set argv {}] pre_impl_debug_tcl]
##     }
##     -post-impl-debug-tcl {
##       set argv [lassign $argv[set argv {}] post_impl_debug_tcl]
##     }
##     -env-var-srcs {
##       set argv [lassign $argv[set argv {}] env_var_srcs]
##     }
##     default {
##       return -code error [list {unknown option} $flag]
##     }
##   }
## }
{unknown option} arty

    while executing
"source [file join $scriptdir "prologue.tcl"]"
    (file "/home/tmpServer/Softwares/chipyard/fpga/fpga-shells/xilinx/common/tcl/vivado.tcl" line 7)
INFO: [Common 17-206] Exiting Vivado at Wed Aug 25 17:14:36 2021...
Makefile:115: recipe for target '/home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/obj/ArtyFPGATestHarness.bit' failed
make: *** [/home/tmpServer/Softwares/chipyard/fpga/generated-src/chipyard.fpga.arty.ArtyFPGATestHarness.TinyRocketArtyConfig/obj/ArtyFPGATestHarness.bit] Error 1

Hi @abejgonzalez , above is the error log I got when I try on Vivado 2020.1. You can notice that the argument for "-ip-vivado-tcls" in the Vivado command is empty. Then, it seems that prologue.tcl will take "-board" as the argument for "-ip-vivado-tcls" and then find an unknown option "arty".

@abejgonzalez
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I understand the issue, I'm just wondering why this is breaking on your end vs. ours. I'm wondering if this issue is just related to Vivado 2020.1 or if this is subject to a different issue. Can you check running on a different Vivado version?

@zslwyuan
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zslwyuan commented Aug 27, 2021

I understand the issue, I'm just wondering why this is breaking on your end vs. ours. I'm wondering if this issue is just related to Vivado 2020.1 or if this is subject to a different issue. Can you check running on a different Vivado version?

I retry the procedure with Vivado 2021.1 and the problem is resolved. It seems that the problem is related to the Vivado Tcl interpreter. I am not sure whetherd the Makefile should be adjusted in case that some users use the old version of Vivado?

@abejgonzalez
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abejgonzalez commented Aug 29, 2021

I guess for now we can switch things around... but in general this shouldn't be an issue... I'll try to see if I have a Vivado 2020.1 laying around to try out next week. Otherwise, I'll go ahead and approve/merge this.

@zslwyuan
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Sure! Maybe indicating the suggested version of Vivado is another solution without changing the Makfile. ^_^

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LGTM to fix 2020.1 Vivado parsing issues. Should still work with other versions of Vivado.

@abejgonzalez abejgonzalez merged commit 984a109 into ucb-bar:dev Aug 30, 2021
@abejgonzalez
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abejgonzalez commented Aug 30, 2021

Thanks for the contribution!

@zslwyuan
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zslwyuan commented Dec 14, 2021

Hi @abejgonzalez and @jamesdunn ,

I modifed the file prologue.tcl in my local project to properly parse the argument of strings with spaces in the string and now it can work with Vivado 2020.1. The problem might be caused by the function definition of "lassign" in Vivado 2020 Tcl parser. I am not sure whether I should update the Tcl file since the problem is fixed in Vivado 2021.

    -ip-vivado-tcls {
      set ip_vivado_tcls {}
      while {[llength $argv]}  {
      	  set firstArg [lindex $argv 0]
      	  set isTclFile [string match *.tcl $firstArg]
      	  if {$isTclFile}   	  {
      	        puts "adding tcl file: ${firstArg}"
      	   	set argv [lassign $argv[set argv {}] firstArg]
      	   	lappend ip_vivado_tcls $firstArg
      	   	puts "tcl file list: ${ip_vivado_tcls}"
      	  } else  {
      	      puts "terminate addition of tcl while argv= ${argv}"
      	      break
      	  }
      }
    }

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2 participants