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Will there be a chiseltest 6.0.0? #699
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There currently is a Note: |
Great! I know that chiseltest (6.0) is not using CIRCT, but it will keep testing alive as it is. We need some more manpower for the verification side on new Chisel. |
As I said in chipsalliance/chisel#3746 I hope this gets resolved. Also my hope is that in the future chisel 7 would get released together with chiseltest 7 and chisel-template 7! |
Is
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You need to have the snapshot resolver enabled in your build.sbt:
I am still planning to release 6.0, just have been pretty busy recently. |
I changed chiselVersion to 6.0.0, chiseltest to 6.0-SNAPSHOT, and the following error occurs with 'sbt test':
I had local firtool version 1.37.0, but upgrading to 1.65.0 didn't change the error. |
@ekiwi so, will chiseltest 6.0.0 keep using the same elaboration steps of chiseltest 5? SFC instead of firtool? |
This might be of interest: chipsalliance/chisel#3746 (comment) |
@gonsolo I see. Then what cases are users supposed to use chiseltest instead of chiselsim? What are the advantages of using chiseltest? However, this is something pretty recent, it was published yesterday. |
None. My (fairly basic) understanding is this: chiseltest will go away, you have svsim which is based on verilator, and now ChiselSim on top of svsim which provides a similar experience as chiseltest (peek & poke, more advanced things like fork/join maybe in the making).
Let's see how it's going to evolve. |
I quickly checked it and I don't see also the support for waveform emission. |
You can do this in Verilator, I guess it's just a matter of adding some support for that in ChiselSim and svsim. Again, I just glanced over this yesterday and I might be wrong. (But if I'm right I believe patches would be welcome. 😄) |
I think I got it, it seems that |
Here we go! Finally a |
Very good! I will try it out tomorrow. Gratulations on your ASPLOS paper! Nice work and nice reading. Cheers, |
The verification story of new Chisel (CIRCT) needs more hands to move forward.
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