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  1. generic-sqed-demo generic-sqed-demo Public

    Verilog 10 3

  2. hslink_phy hslink_phy Public

    Verilog functional model for PHY

    Python 7 6

  3. aqed-dac2020-results aqed-dac2020-results Public

    Source files to reproduce the results shown for A-QED at DAC 2020

    C++ 7 3

  4. case-studies case-studies Public

    Case studies

    Verilog 5 2

  5. aqed-decomp-FMCAD2021 aqed-decomp-FMCAD2021 Public

    Experiments related to our FMCAD 2021 paper "Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition"

    C 5

  6. ridecore-si-checking ridecore-si-checking Public

    Single instruction checking for RIDECORE

    Verilog 3 1

Repositories

Showing 9 of 9 repositories
  • aqed-decomp-FMCAD2021 Public

    Experiments related to our FMCAD 2021 paper "Scaling Up Hardware Accelerator Verification using A-QED with Functional Decomposition"

    upscale-project/aqed-decomp-FMCAD2021’s past year of commit activity
    C 5 0 1 0 Updated Apr 13, 2022
  • eqed-artifact Public
    upscale-project/eqed-artifact’s past year of commit activity
    Python 2 0 2 0 Updated Aug 18, 2021
  • ridecore-si-checking Public

    Single instruction checking for RIDECORE

    upscale-project/ridecore-si-checking’s past year of commit activity
    Verilog 3 1 0 0 Updated Jun 2, 2021
  • generic-sqed-demo Public
    upscale-project/generic-sqed-demo’s past year of commit activity
    Verilog 10 BSD-3-Clause 3 1 0 Updated Feb 6, 2021
  • sqed-generator Public

    Python-based workflow to generate QED modules from ISA/architecture specifications

    upscale-project/sqed-generator’s past year of commit activity
    Verilog 2 3 2 0 Updated Feb 6, 2021
  • cosa2 Public

    Next generation CoSA.

    upscale-project/cosa2’s past year of commit activity
    C++ 3 0 0 0 Updated Jan 27, 2021
  • aqed-dac2020-results Public

    Source files to reproduce the results shown for A-QED at DAC 2020

    upscale-project/aqed-dac2020-results’s past year of commit activity
    C++ 7 3 3 0 Updated Jul 29, 2020
  • case-studies Public

    Case studies

    upscale-project/case-studies’s past year of commit activity
    Verilog 5 2 2 0 Updated Jul 17, 2019
  • hslink_phy Public

    Verilog functional model for PHY

    upscale-project/hslink_phy’s past year of commit activity
    Python 7 BSD-3-Clause 6 0 0 Updated Jun 27, 2019

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