This is my submission for "Reti Logiche" final test at Poitecnico di Milano.
The provided documentation is in italian.
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My project submission for "Reti Logiche" final test, AA 2019/2020.
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Vechus/Working-Zone-Encoder-project-VHDL
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My project submission for "Reti Logiche" final test, AA 2019/2020.
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