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Description
Thanks for taking the time to report this.
Can you please attach an example that shows the issue or missing feature? (Must be openly licensed, completely self-contained so can directly run what you provide. Ideally use test_regress format, see https://veripool.org/guide/latest/contributing.html?highlight=test_regress#reporting-bugs)
`default_nettype none
`timescale 1ns / 1ps
class mockClass;
function void run();
bit [127:0] value;
for(int ii=0; ii<100; ii++) begin
assert(std::randomize(value));
//std::randomize(value);
$display("Value: 0x%h", value);
end
endfunction
endclass
module tb_top();
mockClass Mock;
initial begin
Mock = new();
Mock.run();
$display("TEST PASSED!");
end
endmodule
`default_nettype wire
What output from that test indicates it is wrong, and what is the correct or expected output? (Or, please make test self-checking if possible.)
verilated_random.h:597:15: error: no match for 'operator=' (operand types are 'VlWide<4>' and 'unsigned int')
597 | value = VL_MASK_I(width) & VL_RANDOM_RNG_I(m_rng);
| ~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
What 'verilator' command line do we use to run your example?
verilator -Wall -Wno-fatal -Werror-USERFATAL -Werror-USERERROR --binary --top-module tb_top tb_top.sv
What 'verilator --version' are you using? Did you try it with the git master version? Did you try it with other simulators?
Verilator 5.040 2025-08-30 rev v5.040
Does not work in latest master. Does work in ModelSim/Questa.
What OS and distribution are you using?
Fedora 29
May we assist you in trying to fix this in Verilator yourself?
Any assistance is welcome.
(Please avoid attaching screenshots that show text - you can convert images to text using e.g. https://ocr.space)