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Switching to Non-Blocking Assigns in Single/Dual Port Ram Primitives #3239

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Merged
merged 3 commits into from
Aug 25, 2025
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Merged

Switching to Non-Blocking Assigns in Single/Dual Port Ram Primitives #3239

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2cc2db6
Switched to non-blocking assignments in single and dual port ram prim…
loglav03 Aug 18, 2025
b9b8cb0
Switching to non-blocking assignments in other primitives file
loglav03 Aug 18, 2025
f34cce0
Modifying comments to reflect new changes to single and dual port ram…
loglav03 Aug 18, 2025
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12 changes: 6 additions & 6 deletions parmys/third_party/vtr_flow/primitives.v
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Original file line number Diff line number Diff line change
Expand Up @@ -266,9 +266,9 @@ module single_port_ram #(

always@(posedge clk) begin
if(we) begin
Mem[addr] = data;
Mem[addr] <= data;
end
out = Mem[addr]; //New data read-during write behaviour (blocking assignments)
out <= Mem[addr]; //Old data read-first behaviour (non-blocking assignments)
end

endmodule // single_port_RAM
Expand Down Expand Up @@ -314,16 +314,16 @@ module dual_port_ram #(

always@(posedge clk) begin //Port 1
if(we1) begin
Mem[addr1] = data1;
Mem[addr1] <= data1;
end
out1 = Mem[addr1]; //New data read-during write behaviour (blocking assignments)
out1 <= Mem[addr1]; //Old data read-first behaviour (non-blocking assignments)
end

always@(posedge clk) begin //Port 2
if(we2) begin
Mem[addr2] = data2;
Mem[addr2] <= data2;
end
out2 = Mem[addr2]; //New data read-during write behaviour (blocking assignments)
out2 <= Mem[addr2]; //Old data read-first behaviour (non-blocking assignments)
end

endmodule // dual_port_ram
12 changes: 6 additions & 6 deletions vtr_flow/primitives.v
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Original file line number Diff line number Diff line change
Expand Up @@ -266,9 +266,9 @@ module single_port_ram #(

always@(posedge clk) begin
if(we) begin
Mem[addr] = data;
Mem[addr] <= data;
end
out = Mem[addr]; //New data read-during write behaviour (blocking assignments)
out <= Mem[addr]; //Old data read-first behaviour (non-blocking assignments)
end

endmodule // single_port_RAM
Expand Down Expand Up @@ -314,16 +314,16 @@ module dual_port_ram #(

always@(posedge clk) begin //Port 1
if(we1) begin
Mem[addr1] = data1;
Mem[addr1] <= data1;
end
out1 = Mem[addr1]; //New data read-during write behaviour (blocking assignments)
out1 <= Mem[addr1]; //Old data read-first behaviour (non-blocking assignments)
end

always@(posedge clk) begin //Port 2
if(we2) begin
Mem[addr2] = data2;
Mem[addr2] <= data2;
end
out2 = Mem[addr2]; //New data read-during write behaviour (blocking assignments)
out2 <= Mem[addr2]; //Old data read-first behaviour (non-blocking assignments)
end

endmodule // dual_port_ram