Auto-alignment on comments in PORT declaration

[veripoolbot]

---

Author Name: CHOON LIN LEE
Original Redmine Issue: 1157 from https://www.veripool.org

---

Original Code

module top
(
//Inputs
input CLK, //System Clock
input RST, //Active High Reset
input [3:0] CONTROL, //Control decoder.

//Outputs
output reg [7:0] LIVE_DATA, //1 byte data
output VALID //Valid Flag
);

Is there any feature to auto-align the comments? After auto-align comments, it should be as below:
module top
(
//Inputs
input CLK, //System Clock
input RST, //Active High Reset
input [3:0] CONTROL, //Control decoder.

//Outputs
output reg [7:0] LIVE_DATA,//1 byte data
output VALID //Valid Flag
);

Having issues to align those comments especially the source is from other text editor. EMACS Verilog mode will mis-align the comments for port declaration part.

[veripoolbot]

---

Original Redmine Comment
Author Name: CHOON LIN LEE
Original Date: 2017-04-14T05:57:22Z

---

After auto align the comments, it should be like below:

[veripoolbot]

---

Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-04-26T16:58:48Z

---

I can see the usefulness. If you want to make a patch we'll consider it, otherwise note there is no present active development of new indentation features, so you're in for a long wait.