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JESD204B-Protocol-with-BCH-Error-Correction
JESD204B-Protocol-with-BCH-Error-Correction PublicForked from kaushaldevada-40/JESD204B-Protocol-with-BCH-Error-Correction
Implements a JESD204B high-speed serial link with BCH(31,11) error correction, adding 3-bit random error recovery without altering protocol compliance. Designed in Verilog with modular blocks and s…
SystemVerilog
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FPGA_QPSK-modem
FPGA_QPSK-modem PublicForked from lauchinyuan/FPGA_QPSK-modem
A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
Verilog
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