How to simulate the generated verilog

Hi,

I don't have the hardware ... but I'm interested to compare speedup of result's to understand the code and get an estimate. Can you please tell me how can I do that ?

thanks,
Tarun

[ZFTurbo]

You can try to use testbench:

https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/blob/master/verilog/code/testbench.v

Hi I tried to simulate testbench.v using xcelium by using

xrun -f testbench.v

I encountered the following error :

xrun: *E,FMUK: The type of the file (storage[777]) could not be determined.
xrun: *E,FILEMIS: Cannot find the provided file storage[777].
xrun: *E,FMUK: The type of the file (=) could not be determined.
xrun: *E,FILEMIS: Cannot find the provided file =.
xrun: *E,FMUK: The type of the file (11'b10010111000;) could not be determined.
xrun: *E,FILEMIS: Cannot find the provided file 11'b10010111000;.
xrun: *E,FMUK: The type of the file (storage[778]) could not be determined.
xrun: *E,FILEMIS: Cannot find the provided file storage[778].
xrun: *E,FMUK: The type of the file (=) could not be determined.
xrun: *E,FILEMIS: Cannot find the provided file =.
xrun: *E,FMUK: The type of the file (11'b10010101000;) could not be determined.
xrun: *E,FILEMIS: Cannot find the provided file 11'b10010101000;.
xrun: *E,FMUK: The type of the file (storage[779]) could not be determined.
xrun: *E,FILEMIS: Cannot find the provided file storage[779]

I'm new in field of electronics ... can you suggest How can I run this.

thanks

congrats for the great work,
best wishes

[ZFTurbo]

Do you have access to ModelSim? If I remember we use it for testing.

Hi,

No... I don't have its licence. I only have xcelium.

thanks

I think this is due to not able to access TOP.v file in neuroset. it doesn't include all the .v modules.

thanks

[ZFTurbo]

As I know ModelSim is avilable for free:
https://fpgasoftware.intel.com/?product=modelsim_ae#tabs-2

I can't help you with xcelium. Probably you need to include all needed .v files in testbench somehow.

Thnaks for the modelsim ... I can give a try.
Also I have more query regarding the input image in testbench.v , from which path it's picking its image.

thanks,
Tarun

[ZFTurbo]

It's hardcoded in initial block. See "storage" variable

Hi,
is there any way we can read the image directly by converting it into some format.
also, is this conversion of 11 bits or 10 bits is in testbench is also dynamic based on your previous stage results?

thanks

[ZFTurbo]

Bit for image is found in "r03_find_optimal_bit_for_weights.py". Also there was some code I used to convert PNG to this format used in testbench. I will try to find it.

thanks, Please check and let me know. this will be good so we can see that the output of the simulation is with respect to which image.

thanks

Hi,

One more doubt, the testbench.v is written for :

https://github.com/ZFTurbo/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA/blob/master/verilog/code/neuroset/TOP.v

this file right ?

thanks

[ZFTurbo]

Yes, must be for TOP

Hi,

thanks for your advice ... with some modification, I'm able to finally simulate :) however,
previous error in the compilation is because in neroset/conv_TOP.v file, the parameter conv 3 is not set.
also while simulation is working and result is always 10 and it throws msgs Overflow in conv !.

why result is everytime 10, is it because everytime same test image is hardcoded into testbench.v file ? can you please check.

thanks

Hi,

Congrats, the .py files generating verilog files are written with such precision ... I mean a small change could cause a lot hard to determine errors of the generated files.

kudos for this great work :)

thanks