SG2042: update PCIE driver & downgrade cached to write_combined

Documentation/devicetree/bindings/mfd/syscon.yaml

@@ -115,7 +115,6 @@ select:
           - rockchip,rk3576-qos
           - rockchip,rk3588-qos
           - rockchip,rv1126-qos
-          - sophgo,sg2042-pcie-ctrl
           - st,spear1340-misc
           - stericsson,nomadik-pmu
           - starfive,jh7100-sysmain
@@ -223,7 +222,6 @@ properties:
           - rockchip,rk3576-qos
           - rockchip,rk3588-qos
           - rockchip,rv1126-qos
-          - sophgo,sg2042-pcie-ctrl
           - st,spear1340-misc
           - stericsson,nomadik-pmu
           - starfive,jh7100-sysmain

Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml

@@ -30,78 +30,8 @@ properties:
   device-id:
     const: 0x2042
 
-  msi:
-    type: object
-    $ref: /schemas/interrupt-controller/msi-controller.yaml#
-    unevaluatedProperties: false
-
-    properties:
-      compatible:
-        items:
-          - const: sophgo,sg2042-pcie-msi
-
-      interrupts:
-        maxItems: 1
-
-      interrupt-names:
-        const: msi
-
   msi-parent: true
 
-  sophgo,link-id:
-    $ref: /schemas/types.yaml#/definitions/uint32
-    description: |
-      SG2042 uses Cadence IP, every IP is composed of 2 cores (called link0
-      & link1 as Cadence's term). Each core corresponds to a host bridge,
-      and each host bridge has only one root port. Their configuration
-      registers are completely independent. SG2042 integrates two Cadence IPs,
-      so there can actually be up to four host bridges. "sophgo,link-id" is
-      used to identify which core/link the PCIe host bridge node corresponds to.
-
-      The Cadence IP has two modes of operation, selected by a strap pin.
-
-      In the single-link mode, the Cadence PCIe core instance associated
-      with Link0 is connected to all the lanes and the Cadence PCIe core
-      instance associated with Link1 is inactive.
-
-      In the dual-link mode, the Cadence PCIe core instance associated
-      with Link0 is connected to the lower half of the lanes and the
-      Cadence PCIe core instance associated with Link1 is connected to
-      the upper half of the lanes.
-
-      SG2042 contains 2 Cadence IPs and configures the Cores as below:
-
-                     +-- Core (Link0) <---> pcie_rc0  +-----------------+
-                     |                                |                 |
-      Cadence IP 1 --+                                | cdns_pcie0_ctrl |
-                     |                                |                 |
-                     +-- Core (Link1) <---> disabled  +-----------------+
-
-                     +-- Core (Link0) <---> pcie_rc1  +-----------------+
-                     |                                |                 |
-      Cadence IP 2 --+                                | cdns_pcie1_ctrl |
-                     |                                |                 |
-                     +-- Core (Link1) <---> pcie_rc2  +-----------------+
-
-      pcie_rcX is PCIe node ("sophgo,sg2042-pcie-host") defined in DTS.
-
-      Sophgo defines some new register files to add support for their MSI
-      controller inside PCIe. These new register files are defined in DTS as
-      syscon node ("sophgo,sg2042-pcie-ctrl"), i.e. "cdns_pcie0_ctrl" /
-      "cdns_pcie1_ctrl". cdns_pcieX_ctrl contains some registers shared by
-      pcie_rcX, even two RC (Link)s may share different bits of the same
-      register. For example, cdns_pcie1_ctrl contains registers shared by
-      link0 & link1 for Cadence IP 2.
-
-      "sophgo,link-id" is defined to distinguish the two RC's in one Cadence IP,
-      so we can know what registers (bits) we should use.
-
-  sophgo,syscon-pcie-ctrl:
-    $ref: /schemas/types.yaml#/definitions/phandle
-    description:
-      Phandle to the PCIe System Controller DT node. It's required to
-      access some MSI operation registers shared by PCIe RCs.
-
 allOf:
   - $ref: cdns-pcie-host.yaml#
 
@@ -111,8 +41,6 @@ required:
   - reg-names
   - vendor-id
   - device-id
-  - sophgo,link-id
-  - sophgo,syscon-pcie-ctrl
 
 unevaluatedProperties: false
 
@@ -134,14 +62,5 @@ examples:
       vendor-id = <0x1f1c>;
       device-id = <0x2042>;
       cdns,no-bar-match-nbits = <48>;
-      sophgo,link-id = <0>;
-      sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
-      msi-parent = <&msi_pcie>;
-      msi_pcie: msi {
-        compatible = "sophgo,sg2042-pcie-msi";
-        msi-controller;
-        interrupt-parent = <&intc>;
-        interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
-        interrupt-names = "msi";
-      };
+      msi-parent = <&msi>;
     };

arch/riscv/boot/dts/sophgo/sg2042.dtsi

@@ -262,17 +262,10 @@
 			vendor-id = <0x1f1c>;
 			device-id = <0x2042>;
 			cdns,no-bar-match-nbits = <48>;
-			sophgo,link-id = <0>;
-			sophgo,syscon-pcie-ctrl = <&cdns_pcie0_ctrl>;
 			msi-parent = <&msi>;
 			status = "disabled";
 		};
 
-		cdns_pcie0_ctrl: syscon@7061800000 {
-			compatible = "sophgo,sg2042-pcie-ctrl", "syscon";
-			reg = <0x70 0x61800000 0x0 0x800000>;
-		};
-
 		pcie_rc1: pcie@7062000000 {
 			compatible = "sophgo,sg2042-pcie-host";
 			device_type = "pci";
@@ -291,17 +284,8 @@
 			vendor-id = <0x1f1c>;
 			device-id = <0x2042>;
 			cdns,no-bar-match-nbits = <48>;
-			sophgo,link-id = <0>;
-			sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
-			msi-parent = <&msi_pcie>;
+			msi-parent = <&msi>;
 			status = "disabled";
-			msi_pcie: msi {
-				compatible = "sophgo,sg2042-pcie-msi";
-				msi-controller;
-				interrupt-parent = <&intc>;
-				interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
-				interrupt-names = "msi";
-			};
 		};
 
 		pcie_rc2: pcie@7062800000 {
@@ -322,17 +306,10 @@
 			vendor-id = <0x1f1c>;
 			device-id = <0x2042>;
 			cdns,no-bar-match-nbits = <48>;
-			sophgo,link-id = <1>;
-			sophgo,syscon-pcie-ctrl = <&cdns_pcie1_ctrl>;
 			msi-parent = <&msi>;
 			status = "disabled";
 		};
 
-		cdns_pcie1_ctrl: syscon@7063800000 {
-			compatible = "sophgo,sg2042-pcie-ctrl", "syscon";
-			reg = <0x70 0x63800000 0x0 0x800000>;
-		};
-
 		clint_mswi: interrupt-controller@7094000000 {
 			compatible = "sophgo,sg2042-aclint-mswi", "thead,c900-aclint-mswi";
 			reg = <0x00000070 0x94000000 0x00000000 0x00004000>;

drivers/gpu/drm/ttm/ttm_bo_util.c

@@ -303,6 +303,10 @@ pgprot_t ttm_io_prot(struct ttm_buffer_object *bo, struct ttm_resource *res,
 		caching = res->bus.caching;
 	}
 
+	/* Downgrade cached mapping for non-snooping devices */
+	if (!bo->bdev->dma_coherent && caching == ttm_cached)
+		caching = ttm_write_combined;
+
 	return ttm_prot_from_caching(caching, tmp);
 }
 EXPORT_SYMBOL(ttm_io_prot);

drivers/gpu/drm/ttm/ttm_device.c

@@ -222,6 +222,8 @@ int ttm_device_init(struct ttm_device *bdev, const struct ttm_device_funcs *func
 	list_add_tail(&bdev->device_list, &glob->device_list);
 	mutex_unlock(&ttm_global_mutex);
 
+	bdev->dma_coherent = dev->dma_coherent;
+
 	return 0;
 }
 EXPORT_SYMBOL(ttm_device_init);

drivers/gpu/drm/ttm/ttm_tt.c

@@ -153,6 +153,10 @@ static void ttm_tt_init_fields(struct ttm_tt *ttm,
 			       enum ttm_caching caching,
 			       unsigned long extra_pages)
 {
+	/* Downgrade cached mapping for non-snooping devices */
+	if (!bo->bdev->dma_coherent && caching == ttm_cached)
+		caching = ttm_write_combined;
+
 	ttm->num_pages = (PAGE_ALIGN(bo->base.size) >> PAGE_SHIFT) + extra_pages;
 	ttm->page_flags = page_flags;
 	ttm->dma_address = NULL;

drivers/pci/controller/cadence/Kconfig

@@ -47,7 +47,6 @@ config PCIE_SG2042
 	depends on ARCH_SOPHGO || COMPILE_TEST
 	depends on OF
 	depends on PCI_MSI
-	select IRQ_MSI_LIB
 	select PCIE_CADENCE_HOST
 	help
 	  Say Y here if you want to support the Sophgo SG2042 PCIe platform

drivers/pci/controller/cadence/pcie-cadence-host.c

@@ -531,7 +531,7 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
 	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1);
 	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1);
 
-	if (pcie->ops->cpu_addr_fixup)
+	if (pcie->ops && pcie->ops->cpu_addr_fixup)
 		cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
 
 	addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) |

drivers/pci/controller/cadence/pcie-cadence.c

@@ -92,7 +92,7 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
 	cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1);
 
 	/* Set the CPU address */
-	if (pcie->ops->cpu_addr_fixup)
+	if (pcie->ops && pcie->ops->cpu_addr_fixup)
 		cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
 
 	addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) |
@@ -123,7 +123,7 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
 	}
 
 	/* Set the CPU address */
-	if (pcie->ops->cpu_addr_fixup)
+	if (pcie->ops && pcie->ops->cpu_addr_fixup)
 		cpu_addr = pcie->ops->cpu_addr_fixup(pcie, cpu_addr);
 
 	addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) |

drivers/pci/controller/cadence/pcie-cadence.h

@@ -488,21 +488,21 @@ static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)
 
 static inline int cdns_pcie_start_link(struct cdns_pcie *pcie)
 {
-	if (pcie->ops->start_link)
+	if (pcie->ops && pcie->ops->start_link)
 		return pcie->ops->start_link(pcie);
 
 	return 0;
 }
 
 static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie)
 {
-	if (pcie->ops->stop_link)
+	if (pcie->ops && pcie->ops->stop_link)
 		pcie->ops->stop_link(pcie);
 }
 
 static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie)
 {
-	if (pcie->ops->link_up)
+	if (pcie->ops && pcie->ops->link_up)
 		return pcie->ops->link_up(pcie);
 
 	return true;