UART(Universal Asynnchronous Receiver Transmitter) Design Using Verilog

This is a small project which replicates the UART protocol working to a large extent.
This protocol is commonly used in microcontrollers and microproccesors.
The whole code for this project is written using Verilog HDL and is compiled and checked by Icarus Verilog Compiler and was also simulated in ModelSim.
The main clock used for the UART model is of 50MHz which cn easily be found in any FPGA, if anyone tries to synthesize this model on FPGA.

This project is licensed under the MIT LICENSE.

Contributors

• Adarsh Pal adarshpal999@gmail.com