This repository contains several VHDL codes created for different purposes.
Each file demonstrates a specific digital design or function.
| File Name | Description | 
|---|---|
| adder_timing.vhd | . | 
| array_slices.vhd | . | 
| barrel_shifter.vhd | . | 
| digit_separator.vhd | Splits 123 into 1 2 3 in different variables. | 
| parityDetectorr.vhd | . | 
| pipelining.vhd | . | 
| reg_mux.vhd | . | 
| segment_displayer.vhd | 
- Language: VHDL
- Synthesis: Quartus
- Simulator: ModelSim
This repository is part of my portfolio, showcasing my skills in VHDL programming and digital logic design.
This project is open-source for learning and demonstration purposes.