Info: This is implementation of UART transmit-receive module
Possibilities:
1. Configurable baud rate
2. Configurable data lenght;
3. Configurable parity bit;
4. Configurable stop bit lenght;
FPGA: Xilinx Spartan 6 xc6sl9-2fgt256
Tool: Xilinx ISE 14.7
Dev board: OMMDAZZ
- Run "ISE Design Suite Command Prompt" tool
- Type command: "xtclsh .../src/tcl/create_project.tcl" there '...' means path to repository
- Wait for project and ipcores creating, "Project created!" message will shown in the end.
TODO