MIPS_32_Processor

The goal of this project is to build a 32-bit 5-stage pipelined MIPS-based RISC core based on Harvard Architecture. MIPS ISA (Instruction Set Architecture) was used to develop the MIPS processor, which was divided into three primary modules: datapath unit, control unit, and hazard unit. Two programmes are tested on the processor: GCD calculation of two numbers and Factorial calculation of a number. MIPS assembly code is used to write programmes, which are then translated to machine code. Verilog HDL language is utilised on the Vivado 2022.2 Simulation tool to test the functional simulation of the CPU and compare performance between a five-stage pipelined MIPS processor and a single-cycle MIPS processor. keywords: Pipelined MIPS Processor, Harvard Architecture, MIPS Assembly, Functional Simulation, Datapath, Hazard Unit .