HAL_ChibiOS: add fair scheduling for UARTs

[tridge]

if two UARTs have DMA contention then we can get 2nd UART always
failing to send as as always do sends in the same order per 1kHz
loop. This ensures we give equal priority to all UARTs

see issue #14581

[bugobliterator]

Looks good to me.

[peterbarker]

So I think this patch is reasonable, but it doesn't solve the problem it was intended to. So probably a merge but no backport.

[jschall]

If the DMA is busy when there are bytes to send or receive, the CPU should do it.

[tridge]

If the DMA is busy when there are bytes to send or receive, the CPU should do it.

for recv that can't happen as we don't have receive DMA. For send I agree that it would be nice to switch to interrupt driven when busy

[tridge]

rebased

[yaapu]

@tridge I did some testing on a MatekF405-Wing using UART5 (RX5/TX5) and UART1 (RX1/TX1), I'm logging CRSF telemetry rates every 5 seconds, should be around 150Hz

It looks like the patch does not improve UART5 peformance.

Note: CRSF protocol is hardcoded @416666 baud

    _uart->set_flow_control(AP_HAL::UARTDriver::FLOW_CONTROL_DISABLE);
    _uart->set_unbuffered_writes(true);
    _uart->set_blocking_writes(false);

UART5 with this patch:

APM: RCInput: decoding CRSF
APM: CRSF packet rate 6
APM: CRSF packet rate 12
APM: CRSF packet rate 13
APM: CRSF packet rate 12
APM: CRSF packet rate 10
APM: CRSF packet rate 10
APM: CRSF packet rate 13
APM: CRSF packet rate 14
APM: CRSF packet rate 16
APM: CRSF packet rate 16
APM: CRSF packet rate 11

UART5 without this patch:

APM: RCInput: decoding CRSF
APM: CRSF packet rate 13
APM: CRSF packet rate 23
APM: CRSF packet rate 21
APM: CRSF packet rate 17
APM: CRSF packet rate 22
APM: CRSF packet rate 23
APM: CRSF packet rate 21
APM: CRSF packet rate 22
APM: CRSF packet rate 25
APM: CRSF packet rate 13
APM: CRSF packet rate 27

UART1 with this patch

APM: RCInput: decoding CRSF
APM: CRSF packet rate 125
APM: CRSF packet rate 131
APM: CRSF packet rate 142
APM: CRSF packet rate 144
APM: CRSF packet rate 145
APM: CRSF packet rate 150
APM: CRSF packet rate 133
APM: CRSF packet rate 137

UART1 without this patch

APM: RCInput: decoding CRSF
APM: CRSF packet rate 107
APM: CRSF packet rate 127
APM: CRSF packet rate 143
APM: CRSF packet rate 135
APM: CRSF packet rate 137
APM: CRSF packet rate 137
APM: CRSF packet rate 143

[davidbuzz]

is there any reason this wasnt merged?

[amilcarlucas]

How does this relate to #15984 ?

[andyp1per]

@amilcarlucas this should be fixed by #15984 as I believe we will then rely on the thread scheduling algorithm which tries to be fair.

[IamPete1]

This issue seems to be related to this, #16587

[tridge]

This issue seems to be related to this, #16587

no, I don't think it is related. See fix for that in #16590

[tridge]

rebased, now includes only the dma disable change