UART Protocol Verification Project (SystemVerilog)

📄 Project Overview

This repository contains a SystemVerilog verification environment for a UART protocol implementation. The self-checking testbench generates randomized byte transactions, drives them through the DUT (UART TX/RX), monitors the outputs, and compares sent vs. received data via a scoreboard.

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📁 Repository Structure

env/ # Verification environment components ├── driver.sv ├── generator.sv ├── monitor.sv ├── transaction.sv ├── interface.sv ├── env.sv └── scoreboard.sv

tb/ # Testbench top └── tb_top_uart.sv

rtl/ # DUT RTL files ├── top_uart.sv ├── uart_tx.sv └── uart_rx.sv

package/ # (Optional) verification packages └── uart_pkg.sv

readme.md # Project overview and instructions

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🧠 Modules Description

File	Description
interface.sv	Defines uart_interface with TX/RX signals
transaction.sv	Implements uart_transaction class (rand data, display API)
generator.sv	Sends randomized transactions to the driver
driver.sv	Drives data_in and tx_start and forwards tr to scoreboard
monitor.sv	Samples data_out and rx_done and forwards tr to scoreboard
scoreboard.sv	Compares sent vs. received transactions and logs PASS/FAIL
env.sv	Builds and connects env components using mailboxes
tb_top_uart.sv	Top-level testbench instantiating DUT and environment
top_uart.sv	DUT top integrating uart_tx and uart_rx
uart_tx.sv	UART transmitter implementation
uart_rx.sv	UART receiver implementation
uart_pkg.sv	(Optional) package containing common definitions

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🛠️ Tools & Setup

• Simulator: Icarus Verilog (iverilog)
• Waveform Viewer: GTKWave (gtkwave)
• Editor: VS Code or similar IDE

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⚙️ How to Run Simulation

1. Compile RTL and Testbench
   iverilog -g2012 -o uart_tb rtl/top_uart.sv rtl/uart_tx.sv rtl/uart_rx.sv env/interface.sv env/transaction.sv env/generator.sv env/driver.sv env/monitor.sv env/scoreboard.sv env/env.sv package/uart_pkg.sv tb/tb_top_uart.sv

2. Run Simulation
   vvp uart_tb

3. View Waveform
   gtkwave uart.vcd

Optional: Combine all steps:
iverilog -g2012 -o uart_tb rtl/.sv env/.sv package/.sv tb/.sv && vvp uart_tb && gtkwave uart.vcd

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🎯 Key Features

• Randomized, self-checking testbench using mailboxes
• Parameterized interface for easy extension
• Scoreboard for automated pass/fail checks
• Waveform dumps for detailed debugging
• Clean separation of DUT and verification components

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✒️ Author

Brahma Ganesh Katrapalli – katrapallibrahmaganesh@gmail.com