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2 changes: 1 addition & 1 deletion chipflow_lib/platforms/sim.py
Original file line number Diff line number Diff line change
Expand Up @@ -94,7 +94,7 @@ def build(self, e):
else:
# FIXME: use -defer (workaround for YosysHQ/yosys#4059)
print(f"read_verilog {extra_filename}", file=yosys_file)
print("read_ilang sim_soc.il", file=yosys_file)
print("read_rtlil sim_soc.il", file=yosys_file)
print("hierarchy -top sim_top", file=yosys_file)
# FIXME: use the default -O6 (workaround for YosysHQ/yosys#4227)
print("write_cxxrtl -O4 -header sim_soc.cc", file=yosys_file)
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