Skip to content

Conversation

@robtaylor
Copy link
Contributor

No description provided.

@robtaylor robtaylor requested a review from lanserge February 6, 2025 20:42
@robtaylor robtaylor force-pushed the replace-providers branch 2 times, most recently from e54f570 to 321812e Compare February 10, 2025 22:07
@github-actions
Copy link

github-actions bot commented Feb 10, 2025

PR Preview Action v1.6.0
Preview removed because the pull request was closed.
2025-02-12 18:08 UTC

@ChipFlow ChipFlow deleted a comment from github-actions bot Feb 10, 2025
@robtaylor

This comment was marked as resolved.

@robtaylor

This comment was marked as resolved.

@gatecat

This comment was marked as resolved.

@robtaylor

This comment was marked as resolved.

@robtaylor robtaylor marked this pull request as ready for review February 11, 2025 16:51
In order to remove the need for users to define their own SiliconStep
and pin layout.This introduces a number of mechanisms:

 - PinSignature: a mechanism for Components to label wiring that should
   be routed to pads/pins and the requriments.
 - Pin lock mechanism: addition of `pins` subcommand to `chipflow` cli
   tool. This inspects the top level components and maps the ports to
   pins, with pin behaviour defined by the package definition.
 - Package definitions - basis for package definitions in chipflow-lib
 - General purpose SiliconStep

Still remaining follow on changes are:
 - Encoding power, clock, heartbeat and jtag pin locations in package
   definitions.
 - Pin lock for FPGA boards
 - Removal of need for user to define other steps (sim, software, board,
   export verilog)
@robtaylor robtaylor force-pushed the replace-providers branch 2 times, most recently from efc6091 to db3e8e4 Compare February 12, 2025 15:59
@robtaylor robtaylor merged commit ecb4a9c into main Feb 12, 2025
3 checks passed
@robtaylor robtaylor deleted the replace-providers branch February 12, 2025 18:08
robtaylor pushed a commit that referenced this pull request May 8, 2025
* Send design to ChipFlow API
* Updated sys_clk pad to be clock input

---------

Co-authored-by: Serge Rabyking <serge.rabyking@chipflow.io>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

4 participants