BRAM Yosys memlib file + Supertiles switch matrices doubt

[Dario-CP]

Hello everyone!

I am looking at the SRAM tiles in the fabulous-tiles repository to have a reference to create my own BRAM tile. In the primitives folder of the tile, there is a folder named memlib with a file. I could not find a reference to "memlib" in neither FABulous nor Yosys documentation, so I was wondering if someone could explain me its purpose or point the resource where I could further read about it.

This is the file I am refering to.

Thanks a lot in advance.

[KelvinChung2000]

This is something used by Yosys. It is basically telling yosys what type of memory configuration that your BRAM block can support. Yosys can use that file to gather the memory ports into a single cell, which you can then techmap to the fabric-specific primitive.

https://yosyshq.readthedocs.io/projects/yosys/en/latest/using_yosys/synthesis/memory.html

And the documentation about the file:
https://github.com/YosysHQ/yosys/blob/main/passes/memory/memlib.md

[KelvinChung2000]

The tiles CSV file lists which ports are on the tile, so it shows all possible inputs and outputs to the tile. For the wire span, this is actually more about experimentation and what will provide the best connectivity. If you just want to implement some connectivity, you could use the LUTs tile ports setting as the baseline; that will provide pass-through between east and west to your IO. Then you only need to copy in the top2bot/bot2top signal and connect the macros to the switch matrix.

However, I also do not understand how the connections between the BEL inputs and outputs and the wires is decided, and how the programmable interconnections between them are decided. I guess the inputs of the BEL go from top to bottom and the outputs from bottom to top because the BEL is located in the bottom, but why are only the 8 MSBs of A_DOUT passed from the bottom to the top and not the whole output? What happens with the LSBs? For A_DIN, the LSBs are connected to east wires (I do not know where are those defined. Are they included in that common backbone you mentioned so all switch matrices have them?). However, for A_DOUT, the LSBs are not connected to anything, and I do not understand why.

This is basically a design choice. For the list file, you can think of each line as representing a multiplexer. So, top2bot_A_DIN...,[E2MID0|...] (line 8 on E_IHP_BRAM_top_switch_matrix.list) meaning is a 4-to-1 multplexer connecting to the top2bot_A_DIN[0] port of the tile. Then on A_DIN[15|...],top2bot_A_DIN[7|...] (line 13 on E_IHP_BRAM_bot_switch_matrix.list), this is a compact form of writing a lot of connections; in this case, it is basically connecting the top2bot_A_DIN 8-bit to the top 8-bit of the A_DIN pin of the memory macro. Another way to think about this is you are defining a lot of "1-to-1 multiplexer "

The A_DOUT is connected to bot2top_A_DOUT (line 10 on E_IHP_BRAM_bot_switch_matrix.list), and I assume there are other connections that connect the value to any of the tile ports.

In summary, the designer (Leo in this case) decided that the top 8 bits of A_DIN will always be sourced from the top half of the tile, and the bottom 8 bits from the bottom half. This is purely a design choice.

So if you want more connectivity for where the A_DIN can be sourced from, you could extend the connection to the A_DIN top 8-bit with more input.

[KelvinChung2000]

Improving the switch matrix definition syntax is one of my to-dos. But hope the "a line as a mux" mantle models help for now.

[mole99]

Kelvin is right in that it was a design decision. I essentially replicated the scheme from the DSP tile, driving one half of the bits with the top tile and the other half with the bottom tile. I could have connected the signals differently, but there was no need to since nextpnr was able to route a user design that used of the BRAMs.

[Dario-CP]

Thanks a lot for your answers, but I still do not understand why the BRAM tiles do not include the ports in common/Base.csv
They are not included in their CSVs, but appear in the switch matrices. Additionally, I guess the connectivity would be very bad without those ports. Is that a bug or the common ports should really not be included?

[mole99]

The E_IHP_BRAM/E_IHP_SRAM both have ports only at the west side as you can see here: https://github.com/FPGA-Research/fabulous-tiles/blob/ce6e9233d1df9b182275db1031b462bc2f6dcd2c/tiles/classic/E_IHP_BRAM/E_IHP_BRAM_bot/E_IHP_BRAM_bot.csv#L4-L13
The switch matrix only contains endpoints which started from the east, and startpoints which start from the west.
No, the connectivity is not that bad without those ports. As said, nextpnr was able to route a user design with all of the SRAMs/BRAMs used.
If the connectivity is not good enough for your use case, you can add more multiplexers or add the north/south ports as well. But if all of the SRAMs/BRAMs are allocated, north/south ports won't help much as all the signals come from the west anyway.