Default 'False' output of 0 for Or components #9866
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A good point for having it like that is that gates can shut down when there's no false output, so the result will be more optimal with fewer CPU cycles calculating the logic outputs. However all of the vanilla ships that could make use of this don't. You see loads of OR components chained up with their false outputs set to There is an optimization feature that not even the original developers make use of. Then why keep it around? |
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You seem like the kind of engineer who makes a design with open-collector gates then forgets the pull-up resistors |
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I agree. Any logic gates should start with 0 on the false output, that goes for and, or, xor, greater than, equals and so on. Whenever I place one of those components down, there is a 50% chance i forget to put that 0 in there, because it makes no sense to just have it empty in my head. Null signals are terrible idea in the first place. And after that, i test my circuit and it doesn't work and then i have to click every gate and check the outputs, it's just annoying. If you want a null signal you should opt into that, not out. The definition of OR is that the output is 0 if all inputs are 0, otherwise the output is 1. The way it is by default just isn't like that, and it trips me up every time. |
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I just spent a few hours trying to figure out why my circuits weren't working, until I finally discovered that the Or gate (by default) only functions like half an or gate.
I'm sure there's reasons to have it able to do this, but I can't see any good reason to make wiring more confusing by not making it have a default false output of 0 (and that's not including that if you want to use it a bunch, you'll likely have to set the default output on each one, which get quite tedious)
If there's a way to change default component settings on my client, that'd be wonderful, but I don't see a way to do that either.
Edit: Just discovered that And gates do the same thing. Please?
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