gz_16i8o waveform

When the sel signal goes low, the core accepts a bit stream on the mosi signal and sets the appropriate outputs. Only the hi byte is significant, the low byte is ignored. The testbench sends in a number of bytes and also changes the inputs. You can see the output bitstream change on the miso signal when the inputs change.

Note that as for the other cores with outputs, they are updated immediately as the bits come in. This results in a one serial clock (sclk) skew on each output bit. If we needed all the bits to change together, a register variable would be needed to cache the values until the end of the SPI frame. Timing questions then start to become more complex, since no output bit would be changed until two separate bytes were received across the SPI. On the principle of keep it simple and lower resource usage, the current solution was preferred.