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DMA Bus Conflicts

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Optix edited this page Jan 2, 2021 · 1 revision

Metadata

Source File: /src/tests/dmabusconflict.asm
Compatible with: All models

Description

This test starts an OAM DMA transfer while PC is in the ROM region, causing the CPU to read the transferred data as instructions. Additionally, the test attempts to modify memory during the DMA transfer.

Error Messages

  • No DMA conflicts - The DMA transfer doesn't affect reading from ROM regions
  • DMA bus conflict always reads $FF - While a DMA transfer is active, all reads return $FF instead of the transferred byte
  • Bad instruction timing - Stack operations executed during DMA finish too quickly, executing instructions that would usually be bypassed
  • Invalid register B - Can be caused by DMA starting 2 M-cycles too late or by the first byte of DMA transferred data not being executed
  • Invalid register C - The second or third bytes of DMA data weren't executed

DMG-, MGB- and SGB-exclusive Errors:

  • POP ignores DMA conflict - POP instruction popped data off RAM despite DMA causing bus conflicts
  • DMA allows RAM writes - PUSH instruction pushed data to RAM despite DMA causing bus conflicts

CGB-, AGB- and AGS-exclusive Errors:

  • DMA blocks POP from RAM - POP instruction didn't pop data off RAM even though it should be able to
  • DMA blocks RAM writes - PUSH instruction didn't push data to RAM even though it should be able to

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