@@ -482,7 +482,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
482482 } else {
483483 // Stop transmitting packets and NAK IN xfers.
484484 in_ep [epnum ].diepctl |= USB_DI_SNAK1_M ;
485- while ((in_ep [epnum ].diepint & USB_DI_SNAK1_M ) == 0 ) ;
485+ // while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0) ;
486+ while ((in_ep [epnum ].diepint & USB_D_INEPNAKEFF1_M ) == 0 ) ;
486487
487488 // Disable the endpoint. Note that both SNAK and STALL are set here.
488489 in_ep [epnum ].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M | USB_D_EPDIS1_M );
@@ -492,9 +493,16 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
492493
493494 // Flush the FIFO, and wait until we have confirmed it cleared.
494495 uint8_t const fifo_num = ((in_ep [epnum ].diepctl >> USB_D_TXFNUM1_S ) & USB_D_TXFNUM1_V );
495- USB0 .grstctl |= (fifo_num << USB_TXFNUM_S );
496- USB0 .grstctl |= USB_TXFFLSH_M ;
496+ // USB0.grstctl |= (fifo_num << USB_TXFNUM_S);
497+ // USB0.grstctl |= USB_TXFFLSH_M;
498+ // while ((USB0.grstctl & USB_TXFFLSH_M) != 0) ;
499+ uint32_t rstctl_last = USB0 .grstctl ;
500+ uint32_t rstctl = USB_TXFFLSH_M ;
501+ rstctl |= (fifo_num << USB_TXFNUM_S );
502+ USB0 .grstctl = rstctl ;
497503 while ((USB0 .grstctl & USB_TXFFLSH_M ) != 0 ) ;
504+ USB0 .grstctl = rstctl_last ;
505+ // TODO: Clear grstctl::fifo_num after fifo flsh
498506 } else {
499507 // Only disable currently enabled non-control endpoint
500508 if ((epnum == 0 ) || !(out_ep [epnum ].doepctl & USB_EPENA0_M )) {
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