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APIC Address Incorrect #3

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Jul 22, 2025
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APIC Address Incorrect #3

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4 changes: 2 additions & 2 deletions 02_Architecture/07_APIC.md
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Expand Up @@ -63,10 +63,10 @@ This register contains the following information:
* Bit 8: if set, it means that the processor is the Bootstrap Processor (BSP).
* Bits 9:10: reserved.
* Bit 11: APIC global enable. This bit can be cleared to disable the local APIC for this processor. Realistically there is no reason to do this on modern processors.
* Bits 12:31: Contains the base address of the local APIC for this processor core.
* Bits 12:31: Contains the base address of the local APIC for this processor core. NOTE: The value read from these bits should not be shifted, e.g. if you read ``0xFEE00``, then the address is ``0xFEE00000``, just with bits 0:11 zeroed out.
* Bits 32:63: reserved.

Note that the registers are given as a *physical address*, so to access these we will need to map them somewhere in the virtual address space. This is true for the addresses of any I/O APICs we obtain as well. When the system boots, the base address is usually `0xFEE0000` and often this is the value we read from `rdmsr`. For correct operation the local APIC registers should be mapped as 'strong uncachable'.
Note that the registers are given as a *physical address*, so to access these we will need to map them somewhere in the virtual address space. This is true for the addresses of any I/O APICs we obtain as well. When the system boots, the base address is usually `0xFEE00000` and often this is the value we read from `rdmsr`. For correct operation the local APIC registers should be mapped as 'strong uncachable'.

A complete list of local APIC registers is available in the Intel/AMD software development manuals, but the important ones for now are:

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