Implement Carry Look Ahead Adder (CLA) in Verilog

[Krishnarjunmitra]

📌 Issue Title
Implement Carry Look Ahead Adder (CLA) in Verilog

📝 Description
We need to implement a Carry Look Ahead Adder (CLA) module in Verilog as the next addition to the Adder Series.

Requirements:

• Design a parameterized N-bit Carry Look Ahead Adder (default: 4-bit).
• Use generate and propagate logic to compute carries in parallel.
• Create a Testbench to verify correctness with directed and random test vectors.
• Generate waveforms (using Vivado/ModelSim) and document the results.
• Update README.md under the Completed Projects section once finished.