Cache Coherency & Multicore Processing

In a modern SoC, multiple processors (cores) and peripherals (like DMA controllers) often share the same main memory (DDR/SDRAM). This introduces challenges regarding data visibility and consistency.

Cache Coherency

• The Problem: Each ARM core has its own private, high-speed L1 and L2 caches to reduce the latency of accessing main memory. If Core 0 modifies a variable in shared memory, its change might only be visible in its L1 cache. If Core 1 reads that same variable, it might fetch the old, stale value from its own L1 cache or from main memory.

• The Solution (Coherency Protocol): Hardware mechanisms (like the MESI Protocol – Modified, Exclusive, Shared, Invalid) ensure that all copies of a data block across all caches are consistent. When a core writes to a shared cache line, the protocol automatically invalidates the corresponding cache line in all other caches.

• The Software Task (DMA Interaction): When a peripheral like a DMA (Direct Memory Access) engine writes directly to memory (bypassing the caches), the software must explicitly ensure coherency:

  • Before the CPU reads data written by DMA, the software must issue a Cache Invalidate operation on the corresponding memory range to discard any stale cached data.
  • Before the DMA reads data written by the CPU, the software must issue a Cache Flush/Clean operation to force the CPU's cached data to be written out to main memory.