Interrupts and ISRs (Interrupt Service Routines)

Interrupts are the primary mechanism for hardware to signal the CPU asynchronously.

• Interrupt Latency: The time delay between a hardware event occurring and the CPU starting to execute the first instruction of the corresponding ISR. Minimizing this latency is a major goal in high-performance embedded design.
• ISR Best Practices (The Golden Rules):
  • Keep it Short and Fast: The ISR must finish its work immediately to allow lower-priority interrupts or the main program to resume.
  • void Blocking Calls: Never call functions within an ISR that could block (e.g., functions that wait for a resource, $\text{malloc}$).
  • Minimal Work: The ISR should only perform the absolute minimum task required (e.g., clearing the interrupt source, reading a single data value, and setting a flag).
  • Deferral (Top/Bottom Halves): Complex, time-consuming work should be deferred to a high-priority RTOS task (The Bottom Half) using a signaling mechanism (like a semaphore or message queue). The ISR itself is the Top Half. This separates the time-critical acknowledgement from the heavy data processing.

Context Switch: : when an interrupt occurs, the CPU saves the current context (registers, program counter) before jumping to the ISR. This saved context must be carefully restored when the ISR completes.