boards: st: stm32f4_disco: add support for audio output

The stm32f4_disco board features an audio codec (cs43l22) connected to
an audio jack (TRS) output, and to the stm32f4 via I2S and I2C. To set
this up, several peripherals must be configured:

- Enable I2S3 and the PLLI2S (tuned for 22.05/44.1/88.2 kHz audio)
- Enable DMA1 (used by I2S3)
- Enable I2C1, and add definition for the CS43L22 on the bus
- Disable USART1 and CAN1 which have conflicting pinctrl with I2C1

This new setting is more appropriate, because this gives access to the
audio jack output by default (instead of "bare" pins not connected to
anything on the board).

Signed-off-by: Titouan Christophe <moiandme@gmail.com>

Author: titouanc

boards/st/stm32f4_disco/doc/index.rst

@@ -89,6 +89,12 @@ The Zephyr stm32f4_disco board configuration supports the following hardware fea
 +-----------+------------+-------------------------------------+
 | CAN       | on-chip    | CAN controller                      |
 +-----------+------------+-------------------------------------+
+| I2C       | on-chip    | i2c controller                      |
++-----------+------------+-------------------------------------+
+| I2S       | on-chip    | i2s controller                      |
++-----------+------------+-------------------------------------+
+| AUDIO     | on-board   | audio codec on CS43L22 via I2S3     |
++-----------+------------+-------------------------------------+
 
 .. note:: CAN feature requires CAN transceiver, such as `SK Pang CAN breakout board`_.
           Zephyr default configuration uses CAN_2 exclusively, as simultaneous use
@@ -113,8 +119,6 @@ Default Zephyr Peripheral Mapping:
 
 .. rst-class:: rst-columns
 
-- UART_1_TX : PB6
-- UART_1_RX : PB7
 - UART_2_TX : PA2
 - UART_2_RX : PA3
 - USER_PB : PA0
@@ -124,10 +128,14 @@ Default Zephyr Peripheral Mapping:
 - LD6 : PD15
 - USB DM : PA11
 - USB DP : PA12
-- CAN1_RX : PB8
-- CAN1_TX : PB9
 - CAN2_RX : PB5
 - CAN2_TX : PB13
+- I2C1_SDA : PB9
+- I2C1_SCL : PB6
+- I2S3_MCK : PC7
+- I2S3_CK : PC10
+- I2S3_SD : PC12
+- I2S3_WS : PA4
 
 System Clock
 ============

boards/st/stm32f4_disco/stm32f4_disco.dts

@@ -83,13 +83,6 @@
 	};
 };
 
-&usart1 {
-	pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
-	pinctrl-names = "default";
-	current-speed = <115200>;
-	status = "okay";
-};
-
 &clk_lsi {
 	status = "okay";
 };
@@ -159,12 +152,6 @@ zephyr_udc0: &usbotg_fs {
 	status = "okay";
 };
 
-&can1 {
-	pinctrl-0 = <&can1_rx_pb8 &can1_tx_pb9>;
-	pinctrl-names = "default";
-	status = "disabled";
-};
-
 &can2 {
 	pinctrl-0 = <&can2_rx_pb5 &can2_tx_pb13>;
 	pinctrl-names = "default";
@@ -187,3 +174,42 @@ zephyr_udc0: &usbotg_fs {
 &vbat {
 	status = "okay";
 };
+
+&dma1 {
+	status = "okay";
+};
+
+&plli2s {
+	/* Minimize audio clock error (with i2s mck-enabled) for all of:
+	 * - 22.05kHz / 16b, 24b or 32b
+	 * - 44.1kHz  / 16b, 24b or 32b
+	 * - 88.2kHz  / 16b or 24b
+	 * Note: because the PLLI2S is dependent on the main PLL, the latter
+	 *       should not be changed without checking impact on PLLI2S
+	 */
+	mul-n = <271>;
+	div-r = <2>;
+	status = "okay";
+};
+
+&i2s3 {
+	mck-enabled;
+	pinctrl-0 = <&i2s3_ws_pa4 &i2s3_ck_pc10 &i2s3_sd_pc12 &i2s3_mck_pc7>;
+	pinctrl-names = "default";
+	clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
+		 <&rcc STM32_SRC_PLLI2S_R I2S_SEL(0)>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb9>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	audio_codec: cs43l22@4a {
+		compatible = "cirrus,cs43l22";
+		reg = <0x4a>;
+		reset-gpios = <&gpiod 4 0>;
+	};
+};

doc/releases/migration-guide-4.1.rst

@@ -67,6 +67,10 @@ Boards
   always erase only the sectors of the external flash used by the new firmware,
   and the ``nrfutil`` one would always erase the whole external flash.
 
+* CAN1 and USART1 have been disabled on the ``stm32f4_disco``, because of
+  conflicting pinctrl on I2C1, which is now used to control the audio codec
+  connected to the audio jack output.
+
 Devicetree
 **********