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tiennguyenzgkartben
tiennguyenzg
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drivers: clock control: Initial support for RZ/G3S
Add Clock Control driver support for Renesas RZ/G3S Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com> Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
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‎drivers/clock_control/CMakeLists.txt‎

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@@ -35,6 +35,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SMARTBOND clock_cont
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NUMAKER_SCC clock_control_numaker_scc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_S32 clock_control_nxp_s32.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC clock_control_renesas_ra_cgc.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RZ_CPG clock_control_renesas_rz_cpg.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ clock_control_ambiq.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM clock_control_pwm.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RPI_PICO clock_control_rpi_pico.c)

‎drivers/clock_control/Kconfig‎

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@@ -88,6 +88,8 @@ source "drivers/clock_control/Kconfig.agilex5"
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source "drivers/clock_control/Kconfig.renesas_ra_cgc"
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source "drivers/clock_control/Kconfig.renesas_rz_cpg"
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source "drivers/clock_control/Kconfig.max32"
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source "drivers/clock_control/Kconfig.ambiq"

‎drivers/clock_control/Kconfig.renesas_rz_cpg‎

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# Copyright (c) 2024 Renesas Electronics Corporation
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# SPDX-License-Identifier: Apache-2.0
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config CLOCK_CONTROL_RENESAS_RZ_CPG
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bool "Renesas RZ/G Clock Control Driver"
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default y
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depends on DT_HAS_RENESAS_RZ_CPG_ENABLED
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select USE_RZ_FSP_CPG
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help
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Enable support for Renesas RZ CPG Clock Pulse Generator (CPG) driver.
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The CPG driver supports only module's clocks.
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The PLLs and core clocks are not configured by the CPG driver.

‎drivers/clock_control/clock_control_renesas_rz_cpg.c‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/dt-bindings/clock/renesas_rzg_clock.h>
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#include <zephyr/kernel.h>
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#define DT_DRV_COMPAT renesas_rz_cpg
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static int clock_control_renesas_rz_on(const struct device *dev, clock_control_subsys_t sys)
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{
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if (!dev || !sys) {
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return -EINVAL;
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}
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uint32_t *clock_id = (uint32_t *)sys;
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uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
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uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
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switch (ip) {
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case RZ_IP_GTM:
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R_BSP_MODULE_START(FSP_IP_GTM, ch);
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break;
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case RZ_IP_GPT:
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R_BSP_MODULE_START(FSP_IP_GPT, ch);
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break;
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case RZ_IP_SCIF:
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R_BSP_MODULE_START(FSP_IP_SCIF, ch);
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break;
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case RZ_IP_RIIC:
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R_BSP_MODULE_START(FSP_IP_RIIC, ch);
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break;
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case RZ_IP_RSPI:
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R_BSP_MODULE_START(FSP_IP_RSPI, ch);
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break;
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case RZ_IP_MHU:
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R_BSP_MODULE_START(FSP_IP_MHU, ch);
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break;
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case RZ_IP_DMAC:
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R_BSP_MODULE_START(FSP_IP_DMAC, ch);
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break;
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case RZ_IP_CANFD:
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R_BSP_MODULE_START(FSP_IP_CANFD, ch);
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break;
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case RZ_IP_ADC:
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R_BSP_MODULE_START(FSP_IP_ADC, ch);
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break;
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default:
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return -EINVAL; /* Invalid FSP IP Module */
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}
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return 0;
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}
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static int clock_control_renesas_rz_off(const struct device *dev, clock_control_subsys_t sys)
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{
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if (!dev || !sys) {
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return -EINVAL;
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}
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uint32_t *clock_id = (uint32_t *)sys;
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uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
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uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
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switch (ip) {
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case RZ_IP_GTM:
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R_BSP_MODULE_STOP(FSP_IP_GTM, ch);
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break;
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case RZ_IP_GPT:
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R_BSP_MODULE_STOP(FSP_IP_GPT, ch);
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break;
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case RZ_IP_SCIF:
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R_BSP_MODULE_STOP(FSP_IP_SCIF, ch);
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break;
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case RZ_IP_RIIC:
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R_BSP_MODULE_STOP(FSP_IP_RIIC, ch);
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break;
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case RZ_IP_RSPI:
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R_BSP_MODULE_STOP(FSP_IP_RSPI, ch);
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break;
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case RZ_IP_MHU:
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R_BSP_MODULE_STOP(FSP_IP_MHU, ch);
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break;
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case RZ_IP_DMAC:
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R_BSP_MODULE_STOP(FSP_IP_DMAC, ch);
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break;
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case RZ_IP_CANFD:
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R_BSP_MODULE_STOP(FSP_IP_CANFD, ch);
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break;
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case RZ_IP_ADC:
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R_BSP_MODULE_STOP(FSP_IP_ADC, ch);
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break;
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default:
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return -EINVAL; /* Invalid */
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}
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return 0;
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}
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static int clock_control_renesas_rz_get_rate(const struct device *dev, clock_control_subsys_t sys,
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uint32_t *rate)
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{
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if (!dev || !sys || !rate) {
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return -EINVAL;
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}
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uint32_t *clock_id = (uint32_t *)sys;
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fsp_priv_clock_t clk_src = (*clock_id & RZ_CLOCK_MASK) >> RZ_CLOCK_SHIFT;
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uint32_t clk_div = (*clock_id & RZ_CLOCK_DIV_MASK) >> RZ_CLOCK_DIV_SHIFT;
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uint32_t clk_hz = R_FSP_SystemClockHzGet(clk_src);
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*rate = clk_hz / clk_div;
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return 0;
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}
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static DEVICE_API(clock_control, rz_clock_control_driver_api) = {
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.on = clock_control_renesas_rz_on,
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.off = clock_control_renesas_rz_off,
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.get_rate = clock_control_renesas_rz_get_rate,
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};
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static int clock_control_rz_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0, clock_control_rz_init, NULL, NULL, NULL, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &rz_clock_control_driver_api);

‎dts/bindings/clock/renesas,rz-cpg.yml‎

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# Copyright (c) 2024 Renesas Electronics Corporation24
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# SPDX-License-Identifier: Apache-2.0
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description: RZ Clock Pulse Generator
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compatible: "renesas,rz-cpg"
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include: [base.yaml, clock-controller.yaml]
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properties:
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"#clock-cells":
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const: 1
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clock-cells:
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- clk-id

‎include/zephyr/dt-bindings/clock/renesas_rzg_clock.h‎

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/*
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* Copyright (c) 2024 Renesas Electronics Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZG_CLOCK_H_
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#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZG_CLOCK_H_
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/** RZ clock configuration values */
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#define RZ_IP_MASK 0xFF000000UL
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#define RZ_IP_SHIFT 24UL
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#define RZ_IP_CH_MASK 0xFF0000UL
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#define RZ_IP_CH_SHIFT 16UL
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#define RZ_CLOCK_MASK 0xFF00UL
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#define RZ_CLOCK_SHIFT 8UL
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#define RZ_CLOCK_DIV_MASK 0xFFUL
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#define RZ_CLOCK_DIV_SHIFT 0UL
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#define RZ_IP_GTM 0UL /* General Timer */
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#define RZ_IP_GPT 1UL /* General PWM Timer */
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#define RZ_IP_SCIF 2UL /* Serial Communications Interface with FIFO */
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#define RZ_IP_RIIC 3UL /* I2C Bus Interface */
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#define RZ_IP_RSPI 4UL /* Renesas Serial Peripheral Interface */
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#define RZ_IP_MHU 5UL /* Message Handling Unit */
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#define RZ_IP_DMAC 6UL /* Direct Memory Access Controller */
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#define RZ_IP_CANFD 7UL /* CANFD Interface (RS-CANFD) */
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#define RZ_IP_ADC 8UL /* A/D Converter */
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#define RZ_CLOCK_ICLK 0UL /* Cortex-A55 Clock */
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#define RZ_CLOCK_I2CLK 1UL /* Cortex-M33 Clock */
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#define RZ_CLOCK_I3CLK 2UL /* Cortex-M33 FPU Clock */
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#define RZ_CLOCK_S0CLK 3UL /* DDR-PHY Clock */
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#define RZ_CLOCK_OC0CLK 4UL /* OCTA0 Clock */
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#define RZ_CLOCK_OC1CLK 5UL /* OCTA1 Clock */
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#define RZ_CLOCK_SPI0CLK 6UL /* SPI0 Clock */
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#define RZ_CLOCK_SPI1CLK 7UL /* SPI1 Clock */
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#define RZ_CLOCK_SD0CLK 8UL /* SDH0 Clock */
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#define RZ_CLOCK_SD1CLK 9UL /* SDH1 Clock */
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#define RZ_CLOCK_SD2CLK 10UL /* SDH2 Clock */
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#define RZ_CLOCK_M0CLK 11UL /* VCP LCDC Clock */
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#define RZ_CLOCK_HPCLK 12UL /* Ethernet Clock */
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#define RZ_CLOCK_TSUCLK 13UL /* TSU Clock */
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#define RZ_CLOCK_ZTCLK 14UL /* JAUTH Clock */
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#define RZ_CLOCK_P0CLK 15UL /* APB-BUS Clock */
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#define RZ_CLOCK_P1CLK 16UL /* AXI-BUS Clock */
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#define RZ_CLOCK_P2CLK 17UL /* P2CLK */
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#define RZ_CLOCK_P3CLK 18UL /* P3CLK */
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#define RZ_CLOCK_P4CLK 19UL /* P4CLK */
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#define RZ_CLOCK_P5CLK 20UL /* P5CLK */
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#define RZ_CLOCK_ATCLK 21UL /* ATCLK */
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#define RZ_CLOCK_OSCCLK 22UL /* OSC Clock */
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#define RZ_CLOCK_OSCCLK2 23UL /* OSC2 Clock */
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#define RZ_CLOCK(IP, ch, clk, div) \
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((RZ_IP_##IP << RZ_IP_SHIFT) | ((ch) << RZ_IP_CH_SHIFT) | ((clk) << RZ_CLOCK_SHIFT) | \
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((div) << RZ_CLOCK_DIV_SHIFT))
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/**
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* Pack clock configurations in a 32-bit value
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* as expected for the Device Tree `clocks` property on Renesas RZ/G.
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*
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* @param ch Peripheral channel/unit
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*/
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/* SCIF */
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#define RZ_CLOCK_SCIF(ch) RZ_CLOCK(SCIF, ch, RZ_CLOCK_P0CLK, 1)
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/* GPT */
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#define RZ_CLOCK_GPT(ch) RZ_CLOCK(GPT, ch, RZ_CLOCK_P0CLK, 1)
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/* MHU */
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#define RZ_CLOCK_MHU(ch) RZ_CLOCK(MHU, ch, RZ_CLOCK_P1CLK, 2)
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/* ADC */
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#define RZ_CLOCK_ADC(ch) RZ_CLOCK(ADC, ch, RZ_CLOCK_TSUCLK, 1)
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/* RIIC */
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#define RZ_CLOCK_RIIC(ch) RZ_CLOCK(RIIC, ch, RZ_CLOCK_P0CLK, 1)
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/* GTM */
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#define RZ_CLOCK_GTM(ch) RZ_CLOCK(GTM, ch, RZ_CLOCK_P0CLK, 1)
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/* CAN */
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#define RZ_CLOCK_CANFD(ch) RZ_CLOCK(CANFD, ch, RZ_CLOCK_P4CLK, 2)
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/* RSPI */
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#define RZ_CLOCK_RSPI(ch) RZ_CLOCK(RSPI, ch, RZ_CLOCK_P0CLK, 1)
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/* DMAC */
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#define RZ_CLOCK_DMAC(ch) RZ_CLOCK(DMAC, ch, RZ_CLOCK_P3CLK, 1)
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#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZG_CLOCK_H_ */

‎modules/Kconfig.renesas_fsp‎

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@@ -183,4 +183,9 @@ config USE_RZ_FSP_EXT_IRQ
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help
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Enable RZ FSP External IRQ driver
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config USE_RZ_FSP_CPG
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bool
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help
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Enable RZ FSP CLOCK CONTROL driver
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endif

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