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📝 WalkthroughWalkthroughAdds NVFP4 quantization documentation for Qwen; implements NVFP4 weight/scale padding and trimming in linear NVFP4 paths; and changes attention quantization behavior to skip output scaling when attention output gating is enabled. Changes
Sequence Diagram(s)mermaid mermaid Estimated code review effort🎯 3 (Moderate) | ⏱️ ~25 minutes
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Actionable comments posted: 1
🧹 Nitpick comments (1)
tensorrt_llm/_torch/modules/attention.py (1)
393-396: Document the interaction between quantization scaling and attention output gating.The addition of
and not self.attn_output_gateconditions on lines 393 and 395 bypasses quantization scaling computations when attention output gating is enabled. This is a significant behavioral change that affects how NVFP4 and FP8 quantization interact with attention gating, but there's no explanation for why this is necessary.Add an inline comment explaining this interaction:
out_scale = None out_scale_sf = None + # Skip quantization scaling when attention output gating is enabled to avoid + # interference with the gating operation (sigmoid(gate) * attn_output) if self.has_quant_scale and not self.attn_output_gate: out_scale = self.o_proj.inv_input_scale if self.o_proj.has_nvfp4 and self.support_nvfp4_output and enable_attn_nvfp4_output and not self.attn_output_gate: out_scale_sf = self.o_proj.input_scaleAdditionally, consider logging a warning in
__init__when quantization is enabled with attention output gating, or document this limitation in the docstring.
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has_nvfp4(1923-1926)tensorrt_llm/_torch/modules/fused_moe/interface.py (1)
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support_nvfp4_output(633-634)tensorrt_llm/_torch/attention_backend/trtllm.py (1)
support_nvfp4_output(1362-1365)
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Hi @JadoTu is this PR not meant to be reviewed? (As in seeing draft in its title) |
Hi @venkywonka this PR is decided to be reviewed now. I will change the title:) |
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Actionable comments posted: 2
🧹 Nitpick comments (2)
tensorrt_llm/_torch/modules/attention.py (1)
416-419: Add inline comment explaining scaling bypass for gated attention.The logic now bypasses both
out_scaleandout_scale_sfwhenattn_output_gateis enabled. While this appears intentional for NVFP4 quantization support with gated attention paths, the reasoning is not documented.Consider adding a brief inline comment explaining why quantization scaling should be skipped when output gating is active, as this interaction may not be obvious to future maintainers.
Example:
+ # When attention output gating is enabled, skip quantization scaling + # as the gating operation handles the output scaling differently if self.has_quant_scale and not self.attn_output_gate: out_scale = self.o_proj.inv_input_scaletensorrt_llm/_torch/modules/linear.py (1)
848-850: Optional: Clarify output trimming comment.The comment could be more explicit about why trimming is needed. Consider:
- # Take the dim of out_features if padded. + # Trim output to original out_features size if weight padding was applied if output.shape[-1] > module.out_features: output = output[..., :module.out_features]
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Python classes use PascalCase names.
Functions and methods use snake_case names.
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🧠 Learnings (13)
📓 Common learnings
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation with asserts for total size and TP divisibility.
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation.
Applied to files:
tensorrt_llm/_torch/modules/linear.py
📚 Learning: 2025-09-29T15:14:28.503Z
Learnt from: amitz-nv
Repo: NVIDIA/TensorRT-LLM PR: 8063
File: tensorrt_llm/lora_manager.py:1080-1112
Timestamp: 2025-09-29T15:14:28.503Z
Learning: In tensorrt_llm/lora_manager.py, when calculating part_sizes for attn_qkv fused LoRA modules, the sizes are correctly multiplied by tp_size because model_config.num_heads and model_config.num_kv_heads are already divided by tp_size (per-TP-rank values), so multiplication is needed to get the original full concatenated dimension size. The interleave_fused_lora_weights_for_tp function provides proper validation with asserts for total size and TP divisibility.
Applied to files:
tensorrt_llm/_torch/modules/linear.pytensorrt_llm/_torch/modules/attention.py
📚 Learning: 2025-08-27T17:50:13.264Z
Learnt from: venkywonka
Repo: NVIDIA/TensorRT-LLM PR: 6029
File: .github/pull_request_template.md:45-53
Timestamp: 2025-08-27T17:50:13.264Z
Learning: For PR templates in TensorRT-LLM, avoid suggesting changes that would increase developer overhead, such as converting plain bullets to mandatory checkboxes. The team prefers guidance-style bullets that don't require explicit interaction to reduce friction in the PR creation process.
Applied to files:
examples/models/core/qwen/README.md
📚 Learning: 2025-08-21T00:16:56.457Z
Learnt from: farshadghodsian
Repo: NVIDIA/TensorRT-LLM PR: 7101
File: docs/source/blogs/tech_blog/blog9_Deploying_GPT_OSS_on_TRTLLM.md:36-36
Timestamp: 2025-08-21T00:16:56.457Z
Learning: TensorRT-LLM container release tags in documentation should only reference published NGC container images. The README badge version may be ahead of the actual published container versions.
Applied to files:
examples/models/core/qwen/README.md
📚 Learning: 2025-08-14T23:23:27.449Z
Learnt from: djns99
Repo: NVIDIA/TensorRT-LLM PR: 6915
File: cpp/tensorrt_llm/kernels/cutlass_kernels/moe_gemm/moe_kernels.cu:4010-4012
Timestamp: 2025-08-14T23:23:27.449Z
Learning: For MOE (Mixture of Experts) code reviews in TensorRT-LLM, avoid repeatedly suggesting finalize fusion validation checks and safety assertions. The user djns99 has indicated these suggestions are repetitive and unwanted across multiple MOE-related changes.
Applied to files:
examples/models/core/qwen/README.md
📚 Learning: 2025-09-19T21:28:13.751Z
Learnt from: jhaotingc
Repo: NVIDIA/TensorRT-LLM PR: 7856
File: cpp/tensorrt_llm/thop/fp8BlockScaleMoe.cpp:159-166
Timestamp: 2025-09-19T21:28:13.751Z
Learning: In TensorRT-LLM blockScaleMoe routing (cpp/tensorrt_llm/kernels/trtllmGenKernels/blockScaleMoe/runner.cu), the DeepSeek routing method performs reinterpret_cast<float*>(routingLogits) at line 89, which could cause issues if routing_logits are BF16. However, Qwen3-FP8 models use RenormalizeNaive routing method and are not affected by this dtype casting issue.
Applied to files:
examples/models/core/qwen/README.md
📚 Learning: 2025-08-11T20:09:24.389Z
Learnt from: achartier
Repo: NVIDIA/TensorRT-LLM PR: 6763
File: tests/integration/defs/triton_server/conftest.py:16-22
Timestamp: 2025-08-11T20:09:24.389Z
Learning: In the TensorRT-LLM test infrastructure, the team prefers simple, direct solutions (like hard-coding directory traversal counts) over more complex but robust approaches when dealing with stable directory structures. They accept the maintenance cost of updating tests if the layout changes.
Applied to files:
examples/models/core/qwen/README.md
📚 Learning: 2025-07-28T17:06:08.621Z
Learnt from: moraxu
Repo: NVIDIA/TensorRT-LLM PR: 6303
File: tests/integration/test_lists/qa/examples_test_list.txt:494-494
Timestamp: 2025-07-28T17:06:08.621Z
Learning: In TensorRT-LLM testing, it's common to have both CLI flow tests (test_cli_flow.py) and PyTorch API tests (test_llm_api_pytorch.py) for the same model. These serve different purposes: CLI flow tests validate the traditional command-line workflow, while PyTorch API tests validate the newer LLM API backend. Both are legitimate and should coexist.
Applied to files:
examples/models/core/qwen/README.md
📚 Learning: 2025-08-20T07:43:36.447Z
Learnt from: ChristinaZ
Repo: NVIDIA/TensorRT-LLM PR: 7068
File: cpp/tensorrt_llm/kernels/moeTopKFuncs.cuh:169-172
Timestamp: 2025-08-20T07:43:36.447Z
Learning: In TensorRT-LLM MOE kernels, when processing up to 128 experts across 32 threads, each thread handles at most 4 experts (N < 5 constraint), where N represents candidates per thread rather than total system capacity.
Applied to files:
examples/models/core/qwen/README.md
📚 Learning: 2025-08-01T15:14:45.673Z
Learnt from: yibinl-nvidia
Repo: NVIDIA/TensorRT-LLM PR: 6506
File: examples/models/core/mixtral/requirements.txt:3-3
Timestamp: 2025-08-01T15:14:45.673Z
Learning: In TensorRT-LLM, examples directory can have different dependency versions than the root requirements.txt file. Version conflicts between root and examples dependencies are acceptable because examples are designed to be standalone and self-contained.
Applied to files:
examples/models/core/qwen/README.md
📚 Learning: 2025-09-23T15:12:38.312Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/thop/allreduceOp.cpp:352-446
Timestamp: 2025-09-23T15:12:38.312Z
Learning: In TensorRT-LLM NCCL device implementation, NCCL version 2.28+ requirements are handled at runtime in the nccl_device/config layer rather than with compile-time guards. This allows the allreduceOp to remain version-agnostic and delegates version compatibility validation to the appropriate lower-level components that can gracefully handle unsupported configurations.
Applied to files:
examples/models/core/qwen/README.md
📚 Learning: 2025-09-23T15:13:48.819Z
Learnt from: nv-lschneider
Repo: NVIDIA/TensorRT-LLM PR: 7910
File: cpp/tensorrt_llm/kernels/nccl_device/multimem.h:20-30
Timestamp: 2025-09-23T15:13:48.819Z
Learning: TRT-LLM targets modern CUDA toolkits that support FP8 datatypes, so cuda_fp8.h can be included unconditionally without version guards in TRT-LLM code.
Applied to files:
examples/models/core/qwen/README.md
🪛 GitHub Actions: Release Checks
tensorrt_llm/_torch/modules/linear.py
[error] 745-760: pre-commit: yapf formatting changes were made to the file. The hook failed and requested reformatting. Please review and re-run the pre-commit checks (e.g., 'pre-commit run -a') to ensure passing status.
🔇 Additional comments (2)
examples/models/core/qwen/README.md (1)
881-889: LGTM! Documentation properly structured.The NVFP4 quantization section is now correctly placed under Qwen3-Next with appropriate placeholder paths and clear instructions. This addresses the previous review feedback.
tensorrt_llm/_torch/modules/linear.py (1)
918-918: Consistent integration across weight loading paths.The
weight_and_scale_maybe_padmethod is correctly integrated into all three weight loading paths (vanilla, fused_qkv, fused_gate_up) with consistent calling patterns.Note: Once the documentation and formatting issues in the method itself (lines 748-767) are addressed, this integration will be complete.
Also applies to: 943-943, 980-980
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LGTM
Summary by CodeRabbit
Documentation
Bug Fixes / Improvements
New features: qwen3-next model now can run on nvfp4 format.
Documentation: A quick start of qwen3-next on nvfp4 is added.
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