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Nov 10, 2025
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docs(dn): Lucy Zheng 11/09/2025 #428

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11 changes: 11 additions & 0 deletions src/design_notebooks/2025fall/lz3007.md
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Expand Up @@ -107,4 +107,15 @@ The Control module selects the value of the output signals: WErf, WEdmem, MUXalu

[GitHub: Control Module Code](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/control2.v)

[GitHub: Instruction Memory Code](https://github.com/Ghqlq/Processor-Design-Projects/blob/main/instruction_mem2.v)

**Notes:** There were some modules that were not used for some instructions and I was not sure if I needed to set the value of the signals that corrolate to the unused modules.


## Week 8: 10/27/2025 - 11/02/2025

No tasks were assigned this week.

## Week 9: 10/03/2025 - 10/09/2025

Did not work on onboarding labs this week.