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Nov 17, 2025
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docs(dn):Hongtai_Du_11/06/2025 #429

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Docs(dn):Hongtai_Du_11_05_2025
HongtaiDu Nov 6, 2025
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Merge branch 'NYU-Processor-Design:main' into main
HongtaiDu Nov 10, 2025
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Merge branch 'NYU-Processor-Design:main' into main
HongtaiDu Nov 17, 2025
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21 changes: 21 additions & 0 deletions src/design_notebooks/2025fall/hd2609.md
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Expand Up @@ -48,8 +48,29 @@ Summary: Now all labs are finished. For next week, I will find meeting time with

## Week of October 12th

### Project Work

* Did more Verilog practice questions on the HDLBits. I finished until "Connecting to poarts by position" problem.

Summary: This week I did not meet with team because I was busy with midterms and presentations. I did not have time to meet with team. I have one more midterm next week on Wednesday. I plan to meet with team on Friday or on weekend.

## Week of October 19th

### Project Work

* Did more Verilog practice questions on the HDLBits. I finished until "Adder 1" problem.
* Finished reading lab 5, even if it is incomplete.

Summary: I have one midterm and a presentation to prepare this week, so not a lot progress. Howver, this week I met with team and discussed the next step. I should work on the rest of the labs. Then I will assist other memebers in the future.

## Week of October 26th

### Project Work

* Did more Verilog practice questions on the HDLBits. I finished until "Adder-substractor" problem.
* Started testing some code of Lab 5 in VScode, but met some bugs. It seems due to the version of Verilog. Some code are not supported by the current version installed in my VScode.

Summary: This week I met with team on Wednesday, which is the weekly meeting in this semester. The team will work on Lab 1 and Lab 2 next week. I will prepare to assist on them. Also, due to the bug I met, I plan to debug it next week.